Virtual SMP support for the 34K.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Ralf Baechle
parent
d03d0a5775
commit
340ee4b98c
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@ -1344,6 +1344,14 @@ config CPU_HAS_PREFETCH
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config MIPS_MT
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bool "Enable MIPS MT"
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choice
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prompt "MIPS MT options"
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depends on MIPS_MT
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config MIPS_MT_SMP
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bool "Use 1 TC on each available VPE for SMP"
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select SMP
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config MIPS_VPE_LOADER
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bool "VPE loader support."
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depends on MIPS_MT
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@ -1351,6 +1359,8 @@ config MIPS_VPE_LOADER
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Includes a loader for loading an elf relocatable object
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onto another VPE and running it.
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endchoice
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config MIPS_VPE_LOADER_TOM
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bool "Load VPE program into memory hidden from linux"
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depends on MIPS_VPE_LOADER
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@ -1496,7 +1506,7 @@ source "mm/Kconfig"
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config SMP
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bool "Multi-Processing support"
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depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27
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depends on CPU_RM9000 || (SIBYTE_SB1250 && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP
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---help---
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, like most personal computers, say N. If
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@ -34,6 +34,8 @@ obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_MIPS_MT_SMP) += smp_mt.o
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obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
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obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
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@ -323,6 +323,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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BUILD_HANDLER mdmx mdmx sti silent /* #22 */
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BUILD_HANDLER watch watch sti verbose /* #23 */
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BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
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BUILD_HANDLER mt mt sti verbose /* #25 */
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BUILD_HANDLER dsp dsp sti silent /* #26 */
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BUILD_HANDLER reserved reserved sti verbose /* others */
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@ -0,0 +1,366 @@
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/*
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* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
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*
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* Elizabeth Clarke (beth@mips.com)
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/hardirq.h>
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#include <asm/mmu_context.h>
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#include <asm/smp.h>
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#include <asm/time.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/cacheflush.h>
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#include <asm/mips-boards/maltaint.h>
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#define MIPS_CPU_IPI_RESCHED_IRQ 0
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#define MIPS_CPU_IPI_CALL_IRQ 1
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static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
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#if 0
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static void dump_mtregisters(int vpe, int tc)
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{
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printk("vpe %d tc %d\n", vpe, tc);
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settc(tc);
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printk(" c0 status 0x%lx\n", read_vpe_c0_status());
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printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
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printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0());
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printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus());
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printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart());
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printk(" tcbind 0x%lx\n", read_tc_c0_tcbind());
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printk(" tchalt 0x%lx\n", read_tc_c0_tchalt());
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}
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#endif
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void __init sanitize_tlb_entries(void)
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{
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int i, tlbsiz;
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unsigned long mvpconf0, ncpu;
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if (!cpu_has_mipsmt)
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return;
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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/* Disable TLB sharing */
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clear_c0_mvpcontrol(MVPCONTROL_STLB);
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mvpconf0 = read_c0_mvpconf0();
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printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
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(mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
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(mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
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tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
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ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
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if (tlbsiz > 0) {
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/* share them out across the vpe's */
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tlbsiz /= ncpu;
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printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
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for (i = 0; i < ncpu; i++) {
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settc(i);
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if (i == 0)
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write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
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else
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write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
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(tlbsiz << 25));
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}
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}
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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}
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#if 0
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/*
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* Use c0_MVPConf0 to find out how many CPUs are available, setting up
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* phys_cpu_present_map and the logical/physical mappings.
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*/
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void __init prom_build_cpu_map(void)
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{
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int i, num, ncpus;
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cpus_clear(phys_cpu_present_map);
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/* assume we boot on cpu 0.... */
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cpu_set(0, phys_cpu_present_map);
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__cpu_number_map[0] = 0;
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__cpu_logical_map[0] = 0;
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if (cpu_has_mipsmt) {
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ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1;
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for (i=1, num=0; i< NR_CPUS && i<ncpus; i++) {
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cpu_set(i, phys_cpu_present_map);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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printk(KERN_INFO "%i available secondary CPU(s)\n", num);
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}
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}
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#endif
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static void ipi_resched_dispatch (struct pt_regs *regs)
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{
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do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs);
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}
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static void ipi_call_dispatch (struct pt_regs *regs)
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{
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do_IRQ(MIPS_CPU_IPI_CALL_IRQ, regs);
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}
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irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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return IRQ_HANDLED;
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}
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irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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.flags = SA_INTERRUPT,
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.name = "IPI_resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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.flags = SA_INTERRUPT,
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.name = "IPI_call"
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};
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/*
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* Common setup before any secondaries are started
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* Make sure all CPU's are in a sensible state before we boot any of the
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* secondarys
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*/
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void prom_prepare_cpus(unsigned int max_cpus)
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{
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unsigned long val;
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int i, num;
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if (!cpu_has_mipsmt)
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return;
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/* disable MT so we can configure */
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dvpe();
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dmt();
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/* Put MVPE's into 'configuration state' */
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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val = read_c0_mvpconf0();
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/* we'll always have more TC's than VPE's, so loop setting everything
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to a sensible state */
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for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) {
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settc(i);
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/* VPE's */
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if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
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/* deactivate all but vpe0 */
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if (i != 0) {
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unsigned long tmp = read_vpe_c0_vpeconf0();
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tmp &= ~VPECONF0_VPA;
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/* master VPE */
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tmp |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(tmp);
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/* Record this as available CPU */
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if (i < max_cpus) {
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cpu_set(i, phys_cpu_present_map);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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}
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/* disable multi-threading with TC's */
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write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
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if (i != 0) {
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write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
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write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP);
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/* set config to be the same as vpe0, particularly kseg0 coherency alg */
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write_vpe_c0_config( read_c0_config());
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}
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}
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/* TC's */
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if (i != 0) {
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unsigned long tmp;
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/* bind a TC to each VPE, May as well put all excess TC's
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on the last VPE */
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if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
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write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
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else {
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write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
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/* and set XTC */
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write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
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}
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tmp = read_tc_c0_tcstatus();
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/* mark not allocated and not dynamically allocatable */
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tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
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tmp |= TCSTATUS_IXMT; /* interrupt exempt */
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write_tc_c0_tcstatus(tmp);
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write_tc_c0_tchalt(TCHALT_H);
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}
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}
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/* Release config state */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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/* We'll wait until starting the secondaries before starting MVPE */
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
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/* set up ipi interrupts */
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if (cpu_has_vint) {
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set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
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set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
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}
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cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
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cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
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setup_irq(cpu_ipi_resched_irq, &irq_resched);
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setup_irq(cpu_ipi_call_irq, &irq_call);
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/* need to mark IPI's as IRQ_PER_CPU */
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irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
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irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
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}
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/*
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* Setup the PC, SP, and GP of a secondary processor and start it
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* running!
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* smp_bootstrap is the place to resume from
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* __KSTK_TOS(idle) is apparently the stack pointer
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* (unsigned long)idle->thread_info the gp
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* assumes a 1:1 mapping of TC => VPE
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*/
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void prom_boot_secondary(int cpu, struct task_struct *idle)
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{
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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settc(cpu);
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/* restart */
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write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
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/* enable the tc this vpe/cpu will be running */
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write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
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write_tc_c0_tchalt(0);
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/* enable the VPE */
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write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
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/* stack pointer */
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write_tc_gpr_sp( __KSTK_TOS(idle));
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/* global pointer */
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write_tc_gpr_gp((unsigned long)idle->thread_info);
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flush_icache_range((unsigned long)idle->thread_info,
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(unsigned long)idle->thread_info +
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sizeof(struct thread_info));
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/* finally out of configuration and into chaos */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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evpe(EVPE_ENABLE);
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}
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void prom_init_secondary(void)
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{
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write_c0_status((read_c0_status() & ~ST0_IM ) |
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(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7));
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}
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void prom_smp_finish(void)
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{
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write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
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local_irq_enable();
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}
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void prom_cpus_done(void)
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{
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}
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void core_send_ipi(int cpu, unsigned int action)
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{
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int i;
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unsigned long flags;
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int vpflags;
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local_irq_save (flags);
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vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
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switch (action) {
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case SMP_CALL_FUNCTION:
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i = C_SW1;
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break;
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case SMP_RESCHEDULE_YOURSELF:
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default:
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i = C_SW0;
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break;
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}
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/* 1:1 mapping of vpe and tc... */
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settc(cpu);
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write_vpe_c0_cause(read_vpe_c0_cause() | i);
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evpe(vpflags);
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local_irq_restore(flags);
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}
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@ -28,6 +28,8 @@
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#include <asm/cpu.h>
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#include <asm/dsp.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/module.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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@ -56,6 +58,7 @@ extern asmlinkage void handle_tr(void);
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extern asmlinkage void handle_fpe(void);
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extern asmlinkage void handle_mdmx(void);
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extern asmlinkage void handle_watch(void);
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extern asmlinkage void handle_mt(void);
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extern asmlinkage void handle_dsp(void);
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extern asmlinkage void handle_mcheck(void);
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extern asmlinkage void handle_reserved(void);
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@ -797,6 +800,14 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
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(regs->cp0_status & ST0_TS) ? "" : "not ");
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}
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asmlinkage void do_mt(struct pt_regs *regs)
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{
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die_if_kernel("MIPS MT Thread exception in kernel", regs);
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force_sig(SIGILL, current);
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}
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asmlinkage void do_dsp(struct pt_regs *regs)
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{
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if (cpu_has_dsp)
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@ -1338,6 +1349,9 @@ void __init trap_init(void)
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|||
if (cpu_has_mcheck)
|
||||
set_except_vector(24, handle_mcheck);
|
||||
|
||||
if (cpu_has_mipsmt)
|
||||
set_except_vector(25, handle_mt);
|
||||
|
||||
if (cpu_has_dsp)
|
||||
set_except_vector(26, handle_dsp);
|
||||
|
||||
|
|
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|||
|
|
@ -32,7 +32,7 @@
|
|||
* mknod /dev/vpe0 c 63 0
|
||||
* mknod /dev/vpe1 c 63 1
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/fs.h>
|
||||
|
|
@ -49,6 +49,7 @@
|
|||
#include <linux/poll.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mipsmtregs.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/cpu.h>
|
||||
|
|
@ -697,7 +698,7 @@ int vpe_run(vpe_t * v)
|
|||
dvpe();
|
||||
|
||||
/* Put MVPE's into 'configuration state' */
|
||||
write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_VPC);
|
||||
set_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
if (!list_empty(&v->tc)) {
|
||||
if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
|
||||
|
|
@ -760,7 +761,7 @@ int vpe_run(vpe_t * v)
|
|||
write_vpe_c0_cause(0);
|
||||
|
||||
/* take system out of configuration state */
|
||||
write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_VPC);
|
||||
clear_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
/* clear interrupts enabled IE, ERL, EXL, and KSU from c0 status */
|
||||
write_vpe_c0_status(read_vpe_c0_status() & ~(ST0_ERL | ST0_KSU | ST0_IE | ST0_EXL));
|
||||
|
|
@ -1134,7 +1135,7 @@ int vpe_free(vpe_handle vpe)
|
|||
evpe_flags = dvpe();
|
||||
|
||||
/* Put MVPE's into 'configuration state' */
|
||||
write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_VPC);
|
||||
set_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
settc(t->index);
|
||||
write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
|
||||
|
|
@ -1145,7 +1146,7 @@ int vpe_free(vpe_handle vpe)
|
|||
|
||||
v->state = VPE_STATE_UNUSED;
|
||||
|
||||
write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_VPC);
|
||||
clear_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
evpe(evpe_flags);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1191,7 +1192,7 @@ static int __init vpe_module_init(void)
|
|||
dvpe();
|
||||
|
||||
/* Put MVPE's into 'configuration state' */
|
||||
write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_VPC);
|
||||
set_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
/* dump_mtregs(); */
|
||||
|
||||
|
|
@ -1270,7 +1271,7 @@ static int __init vpe_module_init(void)
|
|||
}
|
||||
|
||||
/* release config state */
|
||||
write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_VPC);
|
||||
clear_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -61,6 +61,15 @@ static unsigned int display_count = 0;
|
|||
static unsigned int timer_tick_count=0;
|
||||
static int mips_cpu_timer_irq;
|
||||
|
||||
static inline void scroll_display_message(void)
|
||||
{
|
||||
if ((timer_tick_count++ % HZ) == 0) {
|
||||
mips_display_message(&display_string[display_count++]);
|
||||
if (display_count == MAX_DISPLAY_COUNT)
|
||||
display_count = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void mips_timer_dispatch (struct pt_regs *regs)
|
||||
{
|
||||
do_IRQ (mips_cpu_timer_irq, regs);
|
||||
|
|
@ -68,17 +77,42 @@ static void mips_timer_dispatch (struct pt_regs *regs)
|
|||
|
||||
irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
if (cpu == 0) {
|
||||
/*
|
||||
* CPU 0 handles the global timer interrupt job and process accounting
|
||||
* resets count/compare registers to trigger next timer int.
|
||||
*/
|
||||
(void) timer_interrupt(irq, dev_id, regs);
|
||||
scroll_display_message();
|
||||
}
|
||||
else {
|
||||
/* Everyone else needs to reset the timer int here as
|
||||
ll_local_timer_interrupt doesn't */
|
||||
/*
|
||||
* FIXME: need to cope with counter underflow.
|
||||
* More support needs to be added to kernel/time for
|
||||
* counter/timer interrupts on multiple CPU's
|
||||
*/
|
||||
write_c0_compare (read_c0_count() + (mips_hpt_frequency/HZ));
|
||||
/*
|
||||
* other CPUs should do profiling and process accounting
|
||||
*/
|
||||
local_timer_interrupt (irq, dev_id, regs);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
#else
|
||||
irqreturn_t r;
|
||||
|
||||
r = timer_interrupt(irq, dev_id, regs);
|
||||
|
||||
if ((timer_tick_count++ % HZ) == 0) {
|
||||
mips_display_message(&display_string[display_count++]);
|
||||
if (display_count == MAX_DISPLAY_COUNT)
|
||||
display_count = 0;
|
||||
}
|
||||
scroll_display_message();
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -176,6 +210,13 @@ void __init mips_timer_setup(struct irqaction *irq)
|
|||
irq->handler = mips_timer_interrupt; /* we use our own handler */
|
||||
setup_irq(mips_cpu_timer_irq, irq);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* irq_desc(riptor) is a global resource, when the interrupt overlaps
|
||||
on seperate cpu's the first one tries to handle the second interrupt.
|
||||
The effect is that the int remains disabled on the second cpu.
|
||||
Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
|
||||
irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
|
||||
#endif
|
||||
|
||||
/* to generate the first timer interrupt */
|
||||
write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#ifndef _ASM_MIPSMTREGS_H
|
||||
#define _ASM_MIPSMTREGS_H
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/war.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
@ -383,6 +384,7 @@ do { \
|
|||
#define read_tc_gpr_gp() mftgpr(28)
|
||||
#define write_tc_gpr_gp(val) mttgpr(28, val)
|
||||
|
||||
__BUILD_SET_C0(mvpcontrol)
|
||||
|
||||
#endif /* Not __ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
|
|
@ -37,8 +37,6 @@
|
|||
#define _ULCAST_ (unsigned long)
|
||||
#endif
|
||||
|
||||
#include <asm/mipsmtregs.h>
|
||||
|
||||
/*
|
||||
* Coprocessor 0 register names
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue