Blackfin: scrub unused watchdog mmr masks
The watchdog code doesn't need these, and the other parts had these punted, so keep the global namespace clean. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -756,40 +756,6 @@
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#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
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/* ********* WATCHDOG TIMER MASKS ******************** */
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/* Watchdog Timer WDOG_CTL Register Masks */
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#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
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#define WDEV_RESET 0x0000 /* generate reset event on roll over */
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#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
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#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
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#define WDEV_NONE 0x0006 /* no event on roll over */
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#define WDEN 0x0FF0 /* enable watchdog */
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#define WDDIS 0x0AD0 /* disable watchdog */
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#define WDRO 0x8000 /* watchdog rolled over latch */
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/* depreciated WDOG_CTL Register Masks for legacy code */
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#define ICTL WDEV
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#define ENABLE_RESET WDEV_RESET
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#define WDOG_RESET WDEV_RESET
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#define ENABLE_NMI WDEV_NMI
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#define WDOG_NMI WDEV_NMI
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#define ENABLE_GPI WDEV_GPI
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#define WDOG_GPI WDEV_GPI
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#define DISABLE_EVT WDEV_NONE
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#define WDOG_NONE WDEV_NONE
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#define TMR_EN WDEN
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#define TMR_DIS WDDIS
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#define TRO WDRO
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#define ICTL_P0 0x01
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#define ICTL_P1 0x02
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#define TRO_P 0x0F
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/* ************** UART CONTROLLER MASKS *************************/
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/* UARTx_LCR Masks */
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#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
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@ -757,40 +757,6 @@
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#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
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/* ********* WATCHDOG TIMER MASKS ******************** */
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/* Watchdog Timer WDOG_CTL Register Masks */
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#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
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#define WDEV_RESET 0x0000 /* generate reset event on roll over */
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#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
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#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
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#define WDEV_NONE 0x0006 /* no event on roll over */
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#define WDEN 0x0FF0 /* enable watchdog */
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#define WDDIS 0x0AD0 /* disable watchdog */
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#define WDRO 0x8000 /* watchdog rolled over latch */
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/* depreciated WDOG_CTL Register Masks for legacy code */
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#define ICTL WDEV
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#define ENABLE_RESET WDEV_RESET
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#define WDOG_RESET WDEV_RESET
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#define ENABLE_NMI WDEV_NMI
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#define WDOG_NMI WDEV_NMI
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#define ENABLE_GPI WDEV_GPI
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#define WDOG_GPI WDEV_GPI
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#define DISABLE_EVT WDEV_NONE
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#define WDOG_NONE WDEV_NONE
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#define TMR_EN WDEN
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#define TMR_DIS WDDIS
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#define TRO WDRO
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#define ICTL_P0 0x01
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#define ICTL_P1 0x02
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#define TRO_P 0x0F
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/* ************** UART CONTROLLER MASKS *************************/
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/* UARTx_LCR Masks */
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#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
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@ -1609,41 +1609,6 @@
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#endif /* _MISRA_RULES */
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/* ********* WATCHDOG TIMER MASKS ******************** */
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/* Watchdog Timer WDOG_CTL Register Masks */
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#ifdef _MISRA_RULES
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#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
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#else
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#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
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#endif /* _MISRA_RULES */
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#define WDEV_RESET 0x0000 /* generate reset event on roll over */
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#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
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#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
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#define WDEV_NONE 0x0006 /* no event on roll over */
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#define WDEN 0x0FF0 /* enable watchdog */
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#define WDDIS 0x0AD0 /* disable watchdog */
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#define WDRO 0x8000 /* watchdog rolled over latch */
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/* deprecated WDOG_CTL Register Masks for legacy code */
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#define ICTL WDEV
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#define ENABLE_RESET WDEV_RESET
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#define WDOG_RESET WDEV_RESET
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#define ENABLE_NMI WDEV_NMI
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#define WDOG_NMI WDEV_NMI
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#define ENABLE_GPI WDEV_GPI
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#define WDOG_GPI WDEV_GPI
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#define DISABLE_EVT WDEV_NONE
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#define WDOG_NONE WDEV_NONE
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#define TMR_EN WDEN
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#define WDOG_DISABLE WDDIS
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#define TRO WDRO
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#define ICTL_P0 0x01
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#define ICTL_P1 0x02
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#define TRO_P 0x0F
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/* ***************************** UART CONTROLLER MASKS ********************** */
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/* UARTx_LCR Register */
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#ifdef _MISRA_RULES
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@ -2092,12 +2092,6 @@
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#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
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#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
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/* Bit masks for WDOG_CTL */
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#define WDEV 0x6 /* Watchdog Event */
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#define WDEN 0xff0 /* Watchdog Enable */
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#define WDRO 0x8000 /* Watchdog Rolled Over */
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/* Bit masks for CNT_CONFIG */
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#define CNTE 0x1 /* Counter Enable */
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