[ARM] 3800/2: S3C2412: DMA channel mappings
DMA channel mappings for the S3C2312 Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Ben Dooks
Russell King
parent
197c9444d6
commit
34348012d6
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@ -34,6 +34,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o
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obj-dma-$(CONFIG_CPU_S3C2412) += s3c2412-dma.o
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#
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# S3C244X support
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@ -0,0 +1,160 @@
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/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c
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*
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* (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2412 DMA selection
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*
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <asm/dma.h>
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#include <asm/arch/dma.h>
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#include <asm/io.h>
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#include "dma.h"
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#include "cpu.h"
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-ac97.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-lcd.h>
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#include <asm/arch/regs-sdi.h>
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#include <asm/arch/regs-iis.h>
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#include <asm/arch/regs-spi.h>
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#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
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static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
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[DMACH_XD0] = {
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.name = "xdreq0",
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.channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
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},
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[DMACH_XD1] = {
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.name = "xdreq1",
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.channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
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},
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[DMACH_SDI] = {
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.name = "sdi",
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.channels = MAP(S3C2412_DMAREQSEL_SDI),
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.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
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.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
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},
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[DMACH_SPI0] = {
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.name = "spi0",
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.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
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.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
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.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
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},
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[DMACH_SPI1] = {
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.name = "spi1",
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.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
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.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
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.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
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},
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[DMACH_UART0] = {
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.name = "uart0",
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.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
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.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
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},
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[DMACH_UART1] = {
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.name = "uart1",
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.channels = MAP(S3C2412_DMAREQSEL_UART1_0),
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.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
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},
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[DMACH_UART2] = {
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.name = "uart2",
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.channels = MAP(S3C2412_DMAREQSEL_UART2_0),
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.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
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},
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[DMACH_UART0_SRC2] = {
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.name = "uart0",
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.channels = MAP(S3C2412_DMAREQSEL_UART0_1),
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.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
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},
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[DMACH_UART1_SRC2] = {
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.name = "uart1",
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.channels = MAP(S3C2412_DMAREQSEL_UART1_1),
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.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
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},
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[DMACH_UART2_SRC2] = {
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.name = "uart2",
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.channels = MAP(S3C2412_DMAREQSEL_UART2_1),
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.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
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.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
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},
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[DMACH_TIMER] = {
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.name = "timer",
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.channels = MAP(S3C2412_DMAREQSEL_TIMER),
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},
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[DMACH_I2S_IN] = {
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.name = "i2s-sdi",
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.channels = MAP(S3C2412_DMAREQSEL_I2SRX),
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.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
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},
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[DMACH_I2S_OUT] = {
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.name = "i2s-sdo",
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.channels = MAP(S3C2412_DMAREQSEL_I2STX),
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.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
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},
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[DMACH_USB_EP1] = {
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.name = "usb-ep1",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP1),
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},
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[DMACH_USB_EP2] = {
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.name = "usb-ep2",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP2),
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},
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[DMACH_USB_EP3] = {
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.name = "usb-ep3",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP3),
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},
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[DMACH_USB_EP4] = {
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.name = "usb-ep4",
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.channels = MAP(S3C2412_DMAREQSEL_USBEP4),
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},
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};
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static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map)
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{
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writel(chan->regs + S3C2412_DMA_DMAREQSEL,
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map->channels[0] | S3C2412_DMAREQSEL_HW);
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}
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static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
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.select = s3c2412_dma_select,
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.dcon_mask = 0,
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.map = s3c2412_dma_mappings,
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.map_size = ARRAY_SIZE(s3c2412_dma_mappings),
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};
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static int s3c2412_dma_add(struct sys_device *sysdev)
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{
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return s3c24xx_dma_init_map(&s3c2412_dma_sel);
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}
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static struct sysdev_driver s3c2412_dma_driver = {
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.add = s3c2412_dma_add,
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};
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static int __init s3c2412_dma_init(void)
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{
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return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
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}
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arch_initcall(s3c2412_dma_init);
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@ -48,6 +48,9 @@ enum dma_ch {
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DMACH_USB_EP2,
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DMACH_USB_EP3,
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DMACH_USB_EP4,
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DMACH_UART0_SRC2, /* s3c2412 second uart sources */
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DMACH_UART1_SRC2,
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DMACH_UART2_SRC2,
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DMACH_MAX, /* the end entry */
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};
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@ -317,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
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#define S3C2410_DMA_DCSRC (0x18)
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#define S3C2410_DMA_DCDST (0x1C)
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#define S3C2410_DMA_DMASKTRIG (0x20)
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#define S3C2412_DMA_DMAREQSEL (0x24)
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#define S3C2410_DISRCC_INC (1<<0)
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#define S3C2410_DISRCC_APB (1<<1)
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@ -383,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
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#define S3C2440_DCON_CH3_PCMOUT (6<<24)
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#endif
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#ifdef CONFIG_CPU_S3C2412
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#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
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#define S3C2412_DMAREQSEL_HW (1)
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#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
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#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
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#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
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#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
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#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
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#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
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#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
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#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
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#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
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#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
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#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
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#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
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#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
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#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
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#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
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#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
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#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
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#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
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#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
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#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
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#endif
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#endif /* __ASM_ARCH_DMA_H */
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