drm/i915: Rearrange GGTT probing to avoid needing a vfunc
Since we have a static if-else-chain for device probing of the global GTT, we do not need to use a function pointer, let alone store it when we never use it again. So use the if-else-chain to call down into the device specific probe. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1470293567-10811-5-git-send-email-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
f6b9d5cabd
commit
34c998b4eb
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@ -2118,7 +2118,6 @@ static void i915_address_space_init(struct i915_address_space *vm,
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struct drm_i915_private *dev_priv)
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{
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drm_mm_init(&vm->mm, vm->start, vm->total);
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vm->dev = &dev_priv->drm;
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INIT_LIST_HEAD(&vm->active_list);
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INIT_LIST_HEAD(&vm->inactive_list);
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list_add_tail(&vm->global_link, &dev_priv->vm_list);
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@ -2921,16 +2920,14 @@ static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
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return (gen9_gmch_ctl - 0xf0 + 1) << 22;
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}
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static int ggtt_probe_common(struct drm_i915_private *dev_priv, size_t gtt_size)
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static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
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{
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struct i915_ggtt *ggtt = &dev_priv->ggtt;
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struct pci_dev *pdev = dev_priv->drm.pdev;
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struct pci_dev *pdev = ggtt->base.dev->pdev;
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struct i915_page_scratch *scratch_page;
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phys_addr_t ggtt_phys_addr;
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phys_addr_t phys_addr;
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/* For Modern GENs the PTEs and register space are split in the BAR */
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ggtt_phys_addr = pci_resource_start(pdev, 0) +
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(pci_resource_len(pdev, 0) / 2);
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phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
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/*
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* On BXT writes larger than 64 bit to the GTT pagetable range will be
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@ -2939,16 +2936,16 @@ static int ggtt_probe_common(struct drm_i915_private *dev_priv, size_t gtt_size)
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* resort to an uncached mapping. The WC issue is easily caught by the
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* readback check when writing GTT PTE entries.
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*/
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if (IS_BROXTON(dev_priv))
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ggtt->gsm = ioremap_nocache(ggtt_phys_addr, gtt_size);
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if (IS_BROXTON(ggtt->base.dev))
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ggtt->gsm = ioremap_nocache(phys_addr, size);
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else
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ggtt->gsm = ioremap_wc(ggtt_phys_addr, gtt_size);
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ggtt->gsm = ioremap_wc(phys_addr, size);
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if (!ggtt->gsm) {
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DRM_ERROR("Failed to map the gtt page table\n");
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DRM_ERROR("Failed to map the ggtt page table\n");
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return -ENOMEM;
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}
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scratch_page = alloc_scratch_page(&dev_priv->drm);
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scratch_page = alloc_scratch_page(ggtt->base.dev);
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if (IS_ERR(scratch_page)) {
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DRM_ERROR("Scratch setup failed\n");
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/* iounmap will also get called at remove, but meh */
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@ -3034,12 +3031,20 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
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}
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static void gen6_gmch_remove(struct i915_address_space *vm)
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{
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struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
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iounmap(ggtt->gsm);
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free_scratch_page(vm->dev, vm->scratch_page);
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}
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static int gen8_gmch_probe(struct i915_ggtt *ggtt)
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{
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struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
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struct pci_dev *pdev = dev_priv->drm.pdev;
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unsigned int size;
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u16 snb_gmch_ctl;
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int ret;
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/* TODO: We're not aware of mappable constraints on gen8 yet */
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ggtt->mappable_base = pci_resource_start(pdev, 2);
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@ -3052,24 +3057,23 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
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if (INTEL_GEN(dev_priv) >= 9) {
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ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
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ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
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size = gen8_get_total_gtt_size(snb_gmch_ctl);
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} else if (IS_CHERRYVIEW(dev_priv)) {
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ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
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ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl);
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size = chv_get_total_gtt_size(snb_gmch_ctl);
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} else {
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ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
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ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
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size = gen8_get_total_gtt_size(snb_gmch_ctl);
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}
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ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
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ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
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if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
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chv_setup_private_ppat(dev_priv);
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else
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bdw_setup_private_ppat(dev_priv);
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ret = ggtt_probe_common(dev_priv, ggtt->size);
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ggtt->base.cleanup = gen6_gmch_remove;
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ggtt->base.bind_vma = ggtt_bind_vma;
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ggtt->base.unbind_vma = ggtt_unbind_vma;
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ggtt->base.insert_page = gen8_ggtt_insert_page;
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@ -3081,15 +3085,15 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
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if (IS_CHERRYVIEW(dev_priv))
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ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
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return ret;
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return ggtt_probe_common(ggtt, size);
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}
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static int gen6_gmch_probe(struct i915_ggtt *ggtt)
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{
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struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
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struct pci_dev *pdev = dev_priv->drm.pdev;
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unsigned int size;
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u16 snb_gmch_ctl;
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int ret;
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ggtt->mappable_base = pci_resource_start(pdev, 2);
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ggtt->mappable_end = pci_resource_len(pdev, 2);
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@ -3097,7 +3101,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
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/* 64/512MB is the current min/max we actually know of, but this is just
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* a coarse sanity check.
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*/
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if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) {
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if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
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DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
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return -ENXIO;
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}
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@ -3107,26 +3111,34 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
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pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
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ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
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ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl);
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ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
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ret = ggtt_probe_common(dev_priv, ggtt->size);
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size = gen6_get_total_gtt_size(snb_gmch_ctl);
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ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
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ggtt->base.clear_range = gen6_ggtt_clear_range;
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ggtt->base.insert_page = gen6_ggtt_insert_page;
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ggtt->base.insert_entries = gen6_ggtt_insert_entries;
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ggtt->base.bind_vma = ggtt_bind_vma;
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ggtt->base.unbind_vma = ggtt_unbind_vma;
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ggtt->base.cleanup = gen6_gmch_remove;
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return ret;
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if (HAS_EDRAM(dev_priv))
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ggtt->base.pte_encode = iris_pte_encode;
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else if (IS_HASWELL(dev_priv))
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ggtt->base.pte_encode = hsw_pte_encode;
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else if (IS_VALLEYVIEW(dev_priv))
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ggtt->base.pte_encode = byt_pte_encode;
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else if (INTEL_GEN(dev_priv) >= 7)
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ggtt->base.pte_encode = ivb_pte_encode;
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else
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ggtt->base.pte_encode = snb_pte_encode;
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return ggtt_probe_common(ggtt, size);
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}
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static void gen6_gmch_remove(struct i915_address_space *vm)
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static void i915_gmch_remove(struct i915_address_space *vm)
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{
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struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base);
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iounmap(ggtt->gsm);
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free_scratch_page(vm->dev, vm->scratch_page);
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intel_gmch_remove();
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}
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static int i915_gmch_probe(struct i915_ggtt *ggtt)
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@ -3149,6 +3161,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
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ggtt->base.clear_range = i915_ggtt_clear_range;
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ggtt->base.bind_vma = ggtt_bind_vma;
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ggtt->base.unbind_vma = ggtt_unbind_vma;
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ggtt->base.cleanup = i915_gmch_remove;
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if (unlikely(ggtt->do_idle_maps))
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DRM_INFO("applying Ironlake quirks for intel_iommu\n");
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@ -3156,11 +3169,6 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
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return 0;
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}
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static void i915_gmch_remove(struct i915_address_space *vm)
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{
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intel_gmch_remove();
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}
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/**
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* i915_ggtt_probe_hw - Probe GGTT hardware location
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* @dev_priv: i915 device
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@ -3170,32 +3178,15 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
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struct i915_ggtt *ggtt = &dev_priv->ggtt;
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int ret;
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if (INTEL_GEN(dev_priv) <= 5) {
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ggtt->probe = i915_gmch_probe;
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ggtt->base.cleanup = i915_gmch_remove;
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} else if (INTEL_GEN(dev_priv) < 8) {
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ggtt->probe = gen6_gmch_probe;
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ggtt->base.cleanup = gen6_gmch_remove;
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if (HAS_EDRAM(dev_priv))
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ggtt->base.pte_encode = iris_pte_encode;
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else if (IS_HASWELL(dev_priv))
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ggtt->base.pte_encode = hsw_pte_encode;
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else if (IS_VALLEYVIEW(dev_priv))
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ggtt->base.pte_encode = byt_pte_encode;
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else if (INTEL_GEN(dev_priv) >= 7)
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ggtt->base.pte_encode = ivb_pte_encode;
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else
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ggtt->base.pte_encode = snb_pte_encode;
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} else {
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ggtt->probe = gen8_gmch_probe;
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ggtt->base.cleanup = gen6_gmch_remove;
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}
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ggtt->base.dev = &dev_priv->drm;
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ggtt->base.is_ggtt = true;
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ret = ggtt->probe(ggtt);
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if (INTEL_GEN(dev_priv) <= 5)
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ret = i915_gmch_probe(ggtt);
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else if (INTEL_GEN(dev_priv) < 8)
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ret = gen6_gmch_probe(ggtt);
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else
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ret = gen8_gmch_probe(ggtt);
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if (ret)
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return ret;
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@ -354,7 +354,6 @@ struct i915_ggtt {
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size_t stolen_usable_size; /* Total size minus BIOS reserved */
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size_t stolen_reserved_base;
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size_t stolen_reserved_size;
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size_t size; /* Total size of Global GTT */
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u64 mappable_end; /* End offset that we can CPU map */
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struct io_mapping *mappable; /* Mapping to our CPU mappable region */
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phys_addr_t mappable_base; /* PA of our GMADR */
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@ -365,8 +364,6 @@ struct i915_ggtt {
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bool do_idle_maps;
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int mtrr;
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int (*probe)(struct i915_ggtt *ggtt);
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};
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struct i915_hw_ppgtt {
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