drm/nvc0/pm: initial implementation of clocks_get()
Not too certain on memory clock yet, but it gets the right numbers for each perflvl on my NVC0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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d0f67a48f4
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354d0781e5
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@ -30,7 +30,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
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nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o \
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nv10_gpio.o nv50_gpio.o \
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nv10_gpio.o nv50_gpio.o \
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nv50_calc.o \
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nv50_calc.o \
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nv04_pm.o nv50_pm.o nva3_pm.o \
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nv04_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o \
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nv50_vram.o nvc0_vram.o \
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nv50_vram.o nvc0_vram.o \
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nv50_vm.o nvc0_vm.o
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nv50_vm.o nvc0_vm.o
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@ -63,6 +63,9 @@ int nva3_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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void *nva3_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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void *nva3_pm_clocks_pre(struct drm_device *, struct nouveau_pm_level *);
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void nva3_pm_clocks_set(struct drm_device *, void *);
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void nva3_pm_clocks_set(struct drm_device *, void *);
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/* nvc0_pm.c */
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int nvc0_pm_clocks_get(struct drm_device *, struct nouveau_pm_level *);
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/* nouveau_temp.c */
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/* nouveau_temp.c */
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void nouveau_temp_init(struct drm_device *dev);
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void nouveau_temp_init(struct drm_device *dev);
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void nouveau_temp_fini(struct drm_device *dev);
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void nouveau_temp_fini(struct drm_device *dev);
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@ -422,6 +422,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->vram.put = nv50_vram_del;
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engine->vram.put = nv50_vram_del;
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engine->vram.flags_valid = nvc0_vram_flags_valid;
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engine->vram.flags_valid = nvc0_vram_flags_valid;
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engine->pm.temp_get = nv84_temp_get;
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engine->pm.temp_get = nv84_temp_get;
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engine->pm.clocks_get = nvc0_pm_clocks_get;
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engine->pm.voltage_get = nouveau_voltage_gpio_get;
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engine->pm.voltage_get = nouveau_voltage_gpio_get;
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engine->pm.voltage_set = nouveau_voltage_gpio_set;
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engine->pm.voltage_set = nouveau_voltage_gpio_set;
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break;
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break;
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145
drivers/gpu/drm/nouveau/nvc0_pm.c
Normal file
145
drivers/gpu/drm/nouveau/nvc0_pm.c
Normal file
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@ -0,0 +1,145 @@
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/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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static u32 read_div(struct drm_device *, int, u32, u32);
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static u32 read_pll(struct drm_device *, u32);
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static u32
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read_vco(struct drm_device *dev, u32 dsrc)
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{
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u32 ssrc = nv_rd32(dev, dsrc);
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if (!(ssrc & 0x00000100))
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return read_pll(dev, 0x00e800);
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return read_pll(dev, 0x00e820);
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}
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static u32
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read_pll(struct drm_device *dev, u32 pll)
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{
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u32 coef = nv_rd32(dev, pll + 4);
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u32 P = (coef & 0x003f0000) >> 16;
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u32 N = (coef & 0x0000ff00) >> 8;
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u32 M = (coef & 0x000000ff) >> 0;
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u32 sclk, doff;
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switch (pll & 0xfff000) {
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case 0x00e000:
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sclk = 27000;
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P = 1;
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break;
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case 0x137000:
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doff = (pll - 0x137000) / 0x20;
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sclk = read_div(dev, doff, 0x137120, 0x137140);
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break;
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case 0x132000:
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switch (pll) {
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case 0x132000:
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sclk = read_pll(dev, 0x132020);
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break;
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case 0x132020:
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sclk = read_div(dev, 0, 0x137320, 0x137330);
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break;
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default:
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return 0;
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}
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break;
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default:
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return 0;
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}
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return sclk * N / M / P;
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}
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static u32
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read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl)
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{
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u32 ssrc = nv_rd32(dev, dsrc + (doff * 4));
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u32 sctl = nv_rd32(dev, dctl + (doff * 4));
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switch (ssrc & 0x00000003) {
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case 0:
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if ((ssrc & 0x00030000) != 0x00030000)
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return 27000;
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return 108000;
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case 2:
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return 100000;
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case 3:
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if (sctl & 0x80000000) {
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u32 sclk = read_vco(dev, dsrc);
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u32 sdiv = (sctl & 0x0000003f) + 2;
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return (sclk * 2) / sdiv;
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}
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return read_vco(dev, dsrc);
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default:
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return 0;
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}
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}
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static u32
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read_mem(struct drm_device *dev)
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{
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u32 ssel = nv_rd32(dev, 0x1373f0);
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if (ssel & 0x00000001)
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return read_div(dev, 0, 0x137300, 0x137310);
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return read_pll(dev, 0x132000);
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}
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static u32
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read_clk(struct drm_device *dev, int clk)
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{
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u32 sctl = nv_rd32(dev, 0x137250 + (clk * 4));
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u32 ssel = nv_rd32(dev, 0x137100);
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u32 sclk, sdiv;
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if (ssel & (1 << clk)) {
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if (clk < 7)
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sclk = read_pll(dev, 0x137000 + (clk * 0x20));
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else
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sclk = read_pll(dev, 0x1370e0);
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sdiv = ((sctl & 0x00003f00) >> 8) + 2;
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} else {
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sclk = read_div(dev, clk, 0x137160, 0x1371d0);
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sdiv = ((sctl & 0x0000003f) >> 0) + 2;
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}
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if (sctl & 0x80000000)
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return (sclk * 2) / sdiv;
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return sclk;
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}
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int
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nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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perflvl->shader = read_clk(dev, 0x00);
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perflvl->core = perflvl->shader / 2;
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perflvl->memory = read_mem(dev);
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perflvl->vdec = read_clk(dev, 0x0e);
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return 0;
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}
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