Merge branch 'pci/host-exynos' into next
* pci/host-exynos: PCI: exynos: Remove redundant of_match_ptr PCI: designware: Add irq_create_mapping() PCI: designware: Make dw_pcie_rd_own_conf(), etc., static PCI: designware: Add header guards PCI: exynos: Add missing clk_disable_unprepare() on error path
This commit is contained in:
Bjorn Helgaas
commit
356bd765e2
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@ -599,18 +599,24 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
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elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
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if (IS_ERR(exynos_pcie->elbi_base))
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return PTR_ERR(exynos_pcie->elbi_base);
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if (IS_ERR(exynos_pcie->elbi_base)) {
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ret = PTR_ERR(exynos_pcie->elbi_base);
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goto fail_bus_clk;
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}
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phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
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if (IS_ERR(exynos_pcie->phy_base))
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return PTR_ERR(exynos_pcie->phy_base);
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if (IS_ERR(exynos_pcie->phy_base)) {
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ret = PTR_ERR(exynos_pcie->phy_base);
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goto fail_bus_clk;
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}
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block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
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if (IS_ERR(exynos_pcie->block_base))
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return PTR_ERR(exynos_pcie->block_base);
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if (IS_ERR(exynos_pcie->block_base)) {
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ret = PTR_ERR(exynos_pcie->block_base);
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goto fail_bus_clk;
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}
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ret = add_pcie_port(pp, pdev);
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if (ret < 0)
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@ -647,7 +653,7 @@ static struct platform_driver exynos_pcie_driver = {
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.driver = {
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.name = "exynos-pcie",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(exynos_pcie_of_match),
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.of_match_table = exynos_pcie_of_match,
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},
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};
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@ -67,7 +67,7 @@
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static struct hw_pci dw_pci;
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unsigned long global_io_offset;
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static unsigned long global_io_offset;
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static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
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{
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@ -118,8 +118,8 @@ static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
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writel(val, pp->dbi_base + reg);
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}
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int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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int ret;
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@ -131,8 +131,8 @@ int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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return ret;
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}
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int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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int ret;
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@ -157,7 +157,7 @@ static struct irq_chip dw_msi_irq_chip = {
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void dw_handle_msi_irq(struct pcie_port *pp)
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{
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unsigned long val;
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int i, pos;
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int i, pos, irq;
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for (i = 0; i < MAX_MSI_CTRLS; i++) {
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
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@ -165,8 +165,9 @@ void dw_handle_msi_irq(struct pcie_port *pp)
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if (val) {
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pos = 0;
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while ((pos = find_next_bit(&val, 32, pos)) != 32) {
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generic_handle_irq(pp->msi_irq_start
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+ (i * 32) + pos);
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irq = irq_find_mapping(pp->irq_domain,
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i * 32 + pos);
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generic_handle_irq(irq);
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pos++;
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}
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}
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@ -237,9 +238,8 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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}
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}
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irq = (pp->msi_irq_start + pos0);
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if ((irq + no_irqs) > (pp->msi_irq_start + MAX_MSI_IRQS-1))
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irq = irq_find_mapping(pp->irq_domain, pos0);
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if (!irq)
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goto no_valid_irq;
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i = 0;
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@ -270,6 +270,7 @@ static void clear_irq(unsigned int irq)
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struct irq_desc *desc;
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struct msi_desc *msi;
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struct pcie_port *pp;
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struct irq_data *data = irq_get_irq_data(irq);
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/* get the port structure */
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desc = irq_to_desc(irq);
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@ -280,7 +281,7 @@ static void clear_irq(unsigned int irq)
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return;
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}
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pos = irq - pp->msi_irq_start;
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pos = data->hwirq;
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irq_free_desc(irq);
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@ -371,8 +372,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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u32 val;
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struct irq_domain *irq_domain;
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int i;
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if (of_pci_range_parser_init(&parser, np)) {
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dev_err(pp->dev, "missing ranges property\n");
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@ -441,15 +441,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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}
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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irq_domain = irq_domain_add_linear(pp->dev->of_node,
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pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
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MAX_MSI_IRQS, &msi_domain_ops,
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&dw_pcie_msi_chip);
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if (!irq_domain) {
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if (!pp->irq_domain) {
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dev_err(pp->dev, "irq domain init failed\n");
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return -ENXIO;
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}
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pp->msi_irq_start = irq_find_mapping(irq_domain, 0);
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for (i = 0; i < MAX_MSI_IRQS; i++)
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irq_create_mapping(pp->irq_domain, i);
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}
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if (pp->ops->host_init)
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@ -667,7 +668,7 @@ static struct pci_ops dw_pcie_ops = {
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.write = dw_pcie_wr_conf,
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};
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int dw_pcie_setup(int nr, struct pci_sys_data *sys)
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static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct pcie_port *pp;
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@ -690,7 +691,7 @@ int dw_pcie_setup(int nr, struct pci_sys_data *sys)
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return 1;
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}
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struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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struct pcie_port *pp = sys_to_pcie(sys);
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@ -707,7 +708,7 @@ struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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return bus;
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}
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int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
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@ -11,6 +11,9 @@
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* published by the Free Software Foundation.
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*/
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#ifndef _PCIE_DESIGNWARE_H
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#define _PCIE_DESIGNWARE_H
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struct pcie_port_info {
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u32 cfg0_size;
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u32 cfg1_size;
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@ -47,7 +50,7 @@ struct pcie_port {
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u32 lanes;
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struct pcie_host_ops *ops;
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int msi_irq;
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int msi_irq_start;
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struct irq_domain *irq_domain;
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unsigned long msi_data;
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DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
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};
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@ -63,17 +66,12 @@ struct pcie_host_ops {
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void (*host_init)(struct pcie_port *pp);
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};
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extern unsigned long global_io_offset;
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int cfg_read(void __iomem *addr, int where, int size, u32 *val);
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int cfg_write(void __iomem *addr, int where, int size, u32 val);
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int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
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int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
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void dw_handle_msi_irq(struct pcie_port *pp);
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void dw_pcie_msi_init(struct pcie_port *pp);
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int dw_pcie_link_up(struct pcie_port *pp);
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void dw_pcie_setup_rc(struct pcie_port *pp);
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int dw_pcie_host_init(struct pcie_port *pp);
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int dw_pcie_setup(int nr, struct pci_sys_data *sys);
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struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
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int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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#endif /* _PCIE_DESIGNWARE_H */
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