avr32: Implement set_rate(), set_parent() and mode() for pll1
This patch is a take two of adding full functionality to PLL1 on AT32AP7000. This allows board-specific code and drivers to configure and enable PLL1. This is useful when precise control over the frequency of e.g. a genclock is needed and requested by users for the ABDAC device. The patch is based upon previous patches from both Haavard Skinnemoen and David Brownell. Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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@ -6,6 +6,7 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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@ -99,6 +100,9 @@ unsigned long at32ap7000_osc_rates[3] = {
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[2] = 12000000,
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};
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static struct clk osc0;
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static struct clk osc1;
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static unsigned long osc_get_rate(struct clk *clk)
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{
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return at32ap7000_osc_rates[clk->index];
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@ -108,9 +112,6 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
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{
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unsigned long div, mul, rate;
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if (!(control & PM_BIT(PLLEN)))
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return 0;
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div = PM_BFEXT(PLLDIV, control) + 1;
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mul = PM_BFEXT(PLLMUL, control) + 1;
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@ -121,6 +122,71 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
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return rate;
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}
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static long pll_set_rate(struct clk *clk, unsigned long rate,
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u32 *pll_ctrl)
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{
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unsigned long mul;
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unsigned long mul_best_fit = 0;
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unsigned long div;
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unsigned long div_min;
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unsigned long div_max;
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unsigned long div_best_fit = 0;
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unsigned long base;
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unsigned long pll_in;
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unsigned long actual = 0;
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unsigned long rate_error;
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unsigned long rate_error_prev = ~0UL;
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u32 ctrl;
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/* Rate must be between 80 MHz and 200 Mhz. */
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if (rate < 80000000UL || rate > 200000000UL)
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return -EINVAL;
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ctrl = PM_BF(PLLOPT, 4);
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base = clk->parent->get_rate(clk->parent);
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/* PLL input frequency must be between 6 MHz and 32 MHz. */
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div_min = DIV_ROUND_UP(base, 32000000UL);
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div_max = base / 6000000UL;
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if (div_max < div_min)
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return -EINVAL;
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for (div = div_min; div <= div_max; div++) {
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pll_in = (base + div / 2) / div;
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mul = (rate + pll_in / 2) / pll_in;
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if (mul == 0)
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continue;
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actual = pll_in * mul;
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rate_error = abs(actual - rate);
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if (rate_error < rate_error_prev) {
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mul_best_fit = mul;
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div_best_fit = div;
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rate_error_prev = rate_error;
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}
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if (rate_error == 0)
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break;
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}
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if (div_best_fit == 0)
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return -EINVAL;
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ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
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ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
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ctrl |= PM_BF(PLLCOUNT, 16);
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if (clk->parent == &osc1)
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ctrl |= PM_BIT(PLLOSC);
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*pll_ctrl = ctrl;
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return actual;
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}
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static unsigned long pll0_get_rate(struct clk *clk)
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{
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u32 control;
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@ -130,6 +196,41 @@ static unsigned long pll0_get_rate(struct clk *clk)
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return pll_get_rate(clk, control);
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}
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static void pll1_mode(struct clk *clk, int enabled)
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{
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unsigned long timeout;
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u32 status;
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u32 ctrl;
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ctrl = pm_readl(PLL1);
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if (enabled) {
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if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
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pr_debug("clk %s: failed to enable, rate not set\n",
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clk->name);
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return;
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}
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ctrl |= PM_BIT(PLLEN);
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pm_writel(PLL1, ctrl);
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/* Wait for PLL lock. */
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for (timeout = 10000; timeout; timeout--) {
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status = pm_readl(ISR);
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if (status & PM_BIT(LOCK1))
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break;
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udelay(10);
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}
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if (!(status & PM_BIT(LOCK1)))
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printk(KERN_ERR "clk %s: timeout waiting for lock\n",
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clk->name);
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} else {
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ctrl &= ~PM_BIT(PLLEN);
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pm_writel(PLL1, ctrl);
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}
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}
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static unsigned long pll1_get_rate(struct clk *clk)
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{
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u32 control;
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@ -139,6 +240,49 @@ static unsigned long pll1_get_rate(struct clk *clk)
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return pll_get_rate(clk, control);
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}
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static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
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{
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u32 ctrl = 0;
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unsigned long actual_rate;
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actual_rate = pll_set_rate(clk, rate, &ctrl);
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if (apply) {
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if (actual_rate != rate)
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return -EINVAL;
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if (clk->users > 0)
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return -EBUSY;
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pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
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clk->name, rate, actual_rate);
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pm_writel(PLL1, ctrl);
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}
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return actual_rate;
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}
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static int pll1_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 ctrl;
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if (clk->users > 0)
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return -EBUSY;
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ctrl = pm_readl(PLL1);
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WARN_ON(ctrl & PM_BIT(PLLEN));
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if (parent == &osc0)
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ctrl &= ~PM_BIT(PLLOSC);
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else if (parent == &osc1)
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ctrl |= PM_BIT(PLLOSC);
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else
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return -EINVAL;
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pm_writel(PLL1, ctrl);
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clk->parent = parent;
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return 0;
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}
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/*
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* The AT32AP7000 has five primary clock sources: One 32kHz
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* oscillator, two crystal oscillators and two PLLs.
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@ -167,7 +311,10 @@ static struct clk pll0 = {
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};
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static struct clk pll1 = {
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.name = "pll1",
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.mode = pll1_mode,
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.get_rate = pll1_get_rate,
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.set_rate = pll1_set_rate,
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.set_parent = pll1_set_parent,
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.parent = &osc0,
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};
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