drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherent
v2: Reorder defines (Ben) v3: More bikesheds, this time re-ordering comments! (Chris) Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Resolve conflict.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -5260,9 +5260,10 @@ enum skl_disp_power_wells {
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/* GEN8 chicken */
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#define HDC_CHICKEN0 0x7300
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#define HDC_FORCE_NON_COHERENT (1<<4)
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#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
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#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
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#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
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#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
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#define HDC_FORCE_NON_COHERENT (1<<4)
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/* WaCatErrorRejectionIssue */
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#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
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@ -788,12 +788,14 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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* workaround for for a possible hang in the unlikely event a TLB
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* invalidation occurs during a PSD flush.
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*/
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/* WaForceEnableNonCoherent:bdw */
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/* WaHdcDisableFetchWhenMasked:bdw */
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/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
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WA_SET_BIT_MASKED(HDC_CHICKEN0,
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/* WaForceEnableNonCoherent:bdw */
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HDC_FORCE_NON_COHERENT |
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/* WaForceContextSaveRestoreNonCoherent:bdw */
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HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
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/* WaHdcDisableFetchWhenMasked:bdw */
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HDC_DONOT_FETCH_MEM_WHEN_MASKED |
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/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
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(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
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/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
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