staging: sm750fb: conform to block comment style
Fix 2 checkpatch errors: -Block comments use * on subsequent lines, -Block comments use a trailing */ on a separate line to conform to block commenting style. Signed-off-by: Elizabeth Ferdman <gnudevliz@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>hifive-unleashed-5.1
Elizabeth Ferdman
Greg Kroah-Hartman
parent
5cf6267915
commit
35e4d8ca05
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@ -2,8 +2,8 @@
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#define DDK750_DISPLAY_H__
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/* panel path select
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80000[29:28]
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*/
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* 80000[29:28]
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*/
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#define PNL_2_OFFSET 0
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#define PNL_2_MASK (3 << PNL_2_OFFSET)
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@ -13,9 +13,9 @@
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/* primary timing & plane enable bit
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1: 80000[8] & 80000[2] on
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0: both off
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*/
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* 1: 80000[8] & 80000[2] on
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* 0: both off
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*/
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#define PRI_TP_OFFSET 4
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#define PRI_TP_MASK BIT(PRI_TP_OFFSET)
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#define PRI_TP_USAGE (PRI_TP_MASK << 16)
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@ -24,8 +24,8 @@
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/* panel sequency status
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80000[27:24]
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*/
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* 80000[27:24]
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*/
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#define PNL_SEQ_OFFSET 6
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#define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
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#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
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@ -33,8 +33,8 @@
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#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
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/* dual digital output
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80000[19]
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*/
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* 80000[19]
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*/
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#define DUAL_TFT_OFFSET 8
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#define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
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#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
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@ -42,9 +42,9 @@
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#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
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/* secondary timing & plane enable bit
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1:80200[8] & 80200[2] on
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0: both off
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*/
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* 1:80200[8] & 80200[2] on
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* 0: both off
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*/
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#define SEC_TP_OFFSET 5
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#define SEC_TP_MASK BIT(SEC_TP_OFFSET)
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#define SEC_TP_USAGE (SEC_TP_MASK << 16)
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@ -52,8 +52,8 @@
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#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
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/* crt path select
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80200[19:18]
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*/
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* 80200[19:18]
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*/
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#define CRT_2_OFFSET 2
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#define CRT_2_MASK (3 << CRT_2_OFFSET)
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#define CRT_2_USAGE (CRT_2_MASK << 16)
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@ -62,8 +62,8 @@
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/* DAC affect both DVI and DSUB
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4[20]
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*/
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* 4[20]
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*/
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#define DAC_OFFSET 7
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#define DAC_MASK BIT(DAC_OFFSET)
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#define DAC_USAGE (DAC_MASK << 16)
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@ -71,8 +71,8 @@
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#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
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/* DPMS only affect D-SUB head
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0[31:30]
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*/
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* 0[31:30]
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*/
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#define DPMS_OFFSET 9
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#define DPMS_MASK (3 << DPMS_OFFSET)
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#define DPMS_USAGE (DPMS_MASK << 16)
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@ -81,19 +81,17 @@
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/*
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LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
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CRT means crt path DSUB
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*/
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/* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
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* CRT means crt path DSUB
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*/
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typedef enum _disp_output_t {
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do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON,
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do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
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do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
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do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
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/*
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do_DSUB_PRI = CRT_2_PRI|PRI_TP_ON|DPMS_ON|DAC_ON,
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do_DSUB_SEC = CRT_2_SEC|SEC_TP_ON|DPMS_ON|DAC_ON,
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*/
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/* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
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* do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON,
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*/
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do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
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do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON,
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}
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@ -21,7 +21,7 @@ unsigned char bus_speed_mode
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POKE32(GPIO_MUX, value);
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/* Enable Hardware I2C power.
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TODO: Check if we need to enable GPIO power?
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* TODO: Check if we need to enable GPIO power?
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*/
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enableI2C(1);
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@ -4,15 +4,14 @@
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#include "ddk750_mode.h"
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#include "ddk750_chip.h"
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/*
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SM750LE only:
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This function takes care extra registers and bit fields required to set
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up a mode in SM750LE
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Explanation about Display Control register:
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HW only supports 7 predefined pixel clocks, and clock select is
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in bit 29:27 of Display Control register.
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*/
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/* SM750LE only:
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* This function takes care extra registers and bit fields required to set
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* up a mode in SM750LE
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*
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* Explanation about Display Control register:
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* HW only supports 7 predefined pixel clocks, and clock select is
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* in bit 29:27 of Display Control register.
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*/
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static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, unsigned long dispControl)
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{
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unsigned long x, y;
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@ -21,9 +20,9 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
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y = pModeParam->vertical_display_end;
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/* SM750LE has to set up the top-left and bottom-right
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registers as well.
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Note that normal SM750/SM718 only use those two register for
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auto-centering mode.
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* registers as well.
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* Note that normal SM750/SM718 only use those two register for
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* auto-centering mode.
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*/
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POKE32(CRT_AUTO_CENTERING_TL, 0);
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@ -33,8 +32,8 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
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((x - 1) & CRT_AUTO_CENTERING_BR_RIGHT_MASK));
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/* Assume common fields in dispControl have been properly set before
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calling this function.
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This function only sets the extra fields in dispControl.
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* calling this function.
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* This function only sets the extra fields in dispControl.
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*/
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/* Clear bit 29:27 of display control register */
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@ -174,8 +174,8 @@ long sii164InitChip(
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i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
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/* De-skew enabled with default 111b value.
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This will fix some artifacts problem in some mode on board 2.2.
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Somehow this fix does not affect board 2.1.
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* This fixes some artifacts problem in some mode on board 2.2.
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* Somehow this fix does not affect board 2.1.
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*/
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if (deskewEnable == 0)
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config = SII164_DESKEW_DISABLE;
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@ -344,7 +344,8 @@ void sii164EnableHotPlugDetection(
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detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT);
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/* Depending on each DVI controller, need to enable the hot plug based on each
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individual chip design. */
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* individual chip design.
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*/
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if (enableHotPlug != 0)
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sii164SelectHotPlugDetectionMode(SII164_HOTPLUG_USE_MDI);
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else
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@ -89,12 +89,12 @@ static void sw_i2c_wait(void)
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* always be non-zero,which makes the while loop
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* never finish.
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* use non-ultimate for loop below is safe
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* */
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*/
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/* Change wait algorithm to use PCI bus clock,
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it's more reliable than counter loop ..
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write 0x61 to 0x3ce and read from 0x3cf
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*/
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* it's more reliable than counter loop ..
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* write 0x61 to 0x3ce and read from 0x3cf
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*/
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int i, tmp;
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for (i = 0; i < 600; i++) {
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@ -501,8 +501,8 @@ long sm750_sw_i2c_write_reg(
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sw_i2c_start();
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/* Send the device address and read the data. All should return success
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in order for the writing processed to be successful
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*/
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* in order for the writing processed to be successful
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*/
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if ((sw_i2c_write_byte(addr) != 0) ||
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(sw_i2c_write_byte(reg) != 0) ||
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(sw_i2c_write_byte(data) != 0)) {
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@ -147,17 +147,17 @@ struct lynxfb_output {
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int dpms;
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int paths;
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/* which paths(s) this output stands for,for sm750:
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paths=1:means output for panel paths
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paths=2:means output for crt paths
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paths=3:means output for both panel and crt paths
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*/
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* paths=1:means output for panel paths
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* paths=2:means output for crt paths
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* paths=3:means output for both panel and crt paths
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*/
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int *channel;
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/* which channel these outputs linked with,for sm750:
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*channel=0 means primary channel
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*channel=1 means secondary channel
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output->channel ==> &crtc->channel
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*/
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* *channel=0 means primary channel
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* *channel=1 means secondary channel
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* output->channel ==> &crtc->channel
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*/
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void *priv;
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int (*proc_setBLANK)(struct lynxfb_output*, int);
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@ -67,7 +67,8 @@ void hw_de_init(struct lynx_accel *accel)
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/* set2dformat only be called from setmode functions
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* but if you need dual framebuffer driver,need call set2dformat
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* every time you use 2d function */
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* every time you use 2d function
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*/
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void hw_set2dformat(struct lynx_accel *accel, int fmt)
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{
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@ -90,7 +91,8 @@ int hw_fillrect(struct lynx_accel *accel,
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if (accel->de_wait() != 0) {
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/* int time wait and always busy,seems hardware
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* got something error */
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* got something error
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*/
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pr_debug("De engine always busy\n");
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return -1;
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}
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@ -152,24 +154,26 @@ unsigned int rop2) /* ROP value */
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/* Determine direction of operation */
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if (sy < dy) {
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/* +----------+
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|S |
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| +----------+
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| | | |
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+---|------+ |
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| D|
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+----------+ */
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* |S |
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* | +----------+
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* | | | |
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* | | | |
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* +---|------+ |
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* | D|
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* +----------+
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*/
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nDirection = BOTTOM_TO_TOP;
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} else if (sy > dy) {
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/* +----------+
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|D |
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| +----------+
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| | | |
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+---|------+ |
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| S|
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+----------+ */
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* |D |
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* | +----------+
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* | | | |
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* | | | |
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* +---|------+ |
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* | S|
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* +----------+
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*/
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nDirection = TOP_TO_BOTTOM;
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} else {
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@ -177,22 +181,24 @@ unsigned int rop2) /* ROP value */
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if (sx <= dx) {
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/* +------+---+------+
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|S | | D|
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+------+---+------+ */
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* |S | | D|
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* | | | |
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* | | | |
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* | | | |
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* +------+---+------+
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*/
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nDirection = RIGHT_TO_LEFT;
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} else {
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/* sx > dx */
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/* +------+---+------+
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|D | | S|
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+------+---+------+ */
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* |D | | S|
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* | | | |
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* | | | |
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* | | | |
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* +------+---+------+
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*/
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nDirection = LEFT_TO_RIGHT;
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}
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@ -208,32 +214,36 @@ unsigned int rop2) /* ROP value */
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}
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/* Note:
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DE_FOREGROUND are DE_BACKGROUND are don't care.
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DE_COLOR_COMPARE and DE_COLOR_COMPARE_MAKS are set by set deSetTransparency().
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* DE_FOREGROUND are DE_BACKGROUND are don't care.
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* DE_COLOR_COMPARE and DE_COLOR_COMPARE_MAKS
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* are set by set deSetTransparency().
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*/
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/* 2D Source Base.
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It is an address offset (128 bit aligned) from the beginning of frame buffer.
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* It is an address offset (128 bit aligned)
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* from the beginning of frame buffer.
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*/
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write_dpr(accel, DE_WINDOW_SOURCE_BASE, sBase); /* dpr40 */
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/* 2D Destination Base.
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It is an address offset (128 bit aligned) from the beginning of frame buffer.
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* It is an address offset (128 bit aligned)
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* from the beginning of frame buffer.
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*/
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write_dpr(accel, DE_WINDOW_DESTINATION_BASE, dBase); /* dpr44 */
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/* Program pitch (distance between the 1st points of two adjacent lines).
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Note that input pitch is BYTE value, but the 2D Pitch register uses
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pixel values. Need Byte to pixel conversion.
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*/
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* Note that input pitch is BYTE value, but the 2D Pitch register uses
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* pixel values. Need Byte to pixel conversion.
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*/
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write_dpr(accel, DE_PITCH,
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((dPitch / Bpp << DE_PITCH_DESTINATION_SHIFT) &
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DE_PITCH_DESTINATION_MASK) |
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(sPitch / Bpp & DE_PITCH_SOURCE_MASK)); /* dpr10 */
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/* Screen Window width in Pixels.
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2D engine uses this value to calculate the linear address in frame buffer for a given point.
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*/
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* 2D engine uses this value to calculate the linear address in frame buffer
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* for a given point.
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*/
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write_dpr(accel, DE_WINDOW_WIDTH,
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((dPitch / Bpp << DE_WINDOW_WIDTH_DST_SHIFT) &
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DE_WINDOW_WIDTH_DST_MASK) |
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@ -307,33 +317,37 @@ int hw_imageblit(struct lynx_accel *accel,
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return -1;
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/* 2D Source Base.
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Use 0 for HOST Blt.
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* Use 0 for HOST Blt.
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*/
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write_dpr(accel, DE_WINDOW_SOURCE_BASE, 0);
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/* 2D Destination Base.
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It is an address offset (128 bit aligned) from the beginning of frame buffer.
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* It is an address offset (128 bit aligned)
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* from the beginning of frame buffer.
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*/
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write_dpr(accel, DE_WINDOW_DESTINATION_BASE, dBase);
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/* Program pitch (distance between the 1st points of two adjacent lines).
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Note that input pitch is BYTE value, but the 2D Pitch register uses
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pixel values. Need Byte to pixel conversion.
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*/
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* Note that input pitch is BYTE value, but the 2D Pitch register uses
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* pixel values. Need Byte to pixel conversion.
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*/
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write_dpr(accel, DE_PITCH,
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((dPitch / bytePerPixel << DE_PITCH_DESTINATION_SHIFT) &
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DE_PITCH_DESTINATION_MASK) |
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(dPitch / bytePerPixel & DE_PITCH_SOURCE_MASK)); /* dpr10 */
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/* Screen Window width in Pixels.
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2D engine uses this value to calculate the linear address in frame buffer for a given point.
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* 2D engine uses this value to calculate the linear address
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* in frame buffer for a given point.
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*/
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write_dpr(accel, DE_WINDOW_WIDTH,
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((dPitch / bytePerPixel << DE_WINDOW_WIDTH_DST_SHIFT) &
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DE_WINDOW_WIDTH_DST_MASK) |
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(dPitch / bytePerPixel & DE_WINDOW_WIDTH_SRC_MASK));
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/* Note: For 2D Source in Host Write, only X_K1_MONO field is needed, and Y_K2 field is not used.
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For mono bitmap, use startBit for X_K1. */
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/* Note: For 2D Source in Host Write, only X_K1_MONO field is needed,
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* and Y_K2 field is not used.
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* For mono bitmap, use startBit for X_K1.
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*/
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write_dpr(accel, DE_SOURCE,
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(startBit << DE_SOURCE_X_K1_SHIFT) &
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DE_SOURCE_X_K1_MONO_MASK); /* dpr00 */
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