mmc: dw_mmc-k3: add sd support for hi3660
Add sd card support for hi3660 soc Signed-off-by: Li Wei <liwei213@huawei.com> Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>hifive-unleashed-5.1
liwei
Ulf Hansson
parent
941e372d89
commit
361c7fe9b0
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@ -8,6 +8,8 @@
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* (at your option) any later version.
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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@ -28,7 +30,35 @@
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#define AO_SCTRL_SEL18 BIT(10)
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#define AO_SCTRL_CTRL3 0x40C
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#define DWMMC_SDIO_ID 2
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#define SOC_SCTRL_SCPERCTRL5 (0x314)
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#define SDCARD_IO_SEL18 BIT(2)
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#define SDCARD_RD_THRESHOLD (512)
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#define GENCLK_DIV (7)
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#define GPIO_CLK_ENABLE BIT(16)
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#define GPIO_CLK_DIV_MASK GENMASK(11, 8)
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#define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13)
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#define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
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#define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21)
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#define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26)
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#define TIMING_MODE 3
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#define TIMING_CFG_NUM 10
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#define NUM_PHASES (40)
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#define ENABLE_SHIFT_MIN_SMPL (4)
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#define ENABLE_SHIFT_MAX_SMPL (12)
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#define USE_DLY_MIN_SMPL (11)
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#define USE_DLY_MAX_SMPL (14)
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struct k3_priv {
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int ctrl_id;
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u32 cur_speed;
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struct regmap *reg;
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};
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@ -38,6 +68,41 @@ static unsigned long dw_mci_hi6220_caps[] = {
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0
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};
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struct hs_timing {
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u32 drv_phase;
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u32 smpl_dly;
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u32 smpl_phase_max;
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u32 smpl_phase_min;
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};
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struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
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{ /* reserved */ },
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{ /* SD */
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{7, 0, 15, 15,}, /* 0: LEGACY 400k */
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{6, 0, 4, 4,}, /* 1: MMC_HS */
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{6, 0, 3, 3,}, /* 2: SD_HS */
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{6, 0, 15, 15,}, /* 3: SDR12 */
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{6, 0, 2, 2,}, /* 4: SDR25 */
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{4, 0, 11, 0,}, /* 5: SDR50 */
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{6, 4, 15, 0,}, /* 6: SDR104 */
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{0}, /* 7: DDR50 */
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{0}, /* 8: DDR52 */
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{0}, /* 9: HS200 */
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},
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{ /* SDIO */
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{7, 0, 15, 15,}, /* 0: LEGACY 400k */
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{0}, /* 1: MMC_HS */
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{6, 0, 15, 15,}, /* 2: SD_HS */
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{6, 0, 15, 15,}, /* 3: SDR12 */
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{6, 0, 0, 0,}, /* 4: SDR25 */
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{4, 0, 12, 0,}, /* 5: SDR50 */
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{5, 4, 15, 0,}, /* 6: SDR104 */
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{0}, /* 7: DDR50 */
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{0}, /* 8: DDR52 */
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{0}, /* 9: HS200 */
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}
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};
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static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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int ret;
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@ -66,6 +131,10 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
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if (IS_ERR(priv->reg))
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priv->reg = NULL;
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priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
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if (priv->ctrl_id < 0)
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priv->ctrl_id = 0;
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host->priv = priv;
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return 0;
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}
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@ -144,7 +213,236 @@ static const struct dw_mci_drv_data hi6220_data = {
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.execute_tuning = dw_mci_hi6220_execute_tuning,
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};
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static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
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int smpl_phase)
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{
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u32 drv_phase;
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u32 smpl_dly;
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u32 use_smpl_dly = 0;
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u32 enable_shift = 0;
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u32 reg_value;
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int ctrl_id;
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struct k3_priv *priv;
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priv = host->priv;
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ctrl_id = priv->ctrl_id;
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drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
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smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly;
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if (smpl_phase == -1)
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smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
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hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
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switch (timing) {
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case MMC_TIMING_UHS_SDR104:
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if (smpl_phase >= USE_DLY_MIN_SMPL &&
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smpl_phase <= USE_DLY_MAX_SMPL)
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use_smpl_dly = 1;
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/* fallthrough */
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case MMC_TIMING_UHS_SDR50:
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if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
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smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
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enable_shift = 1;
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break;
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}
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mci_writel(host, GPIO, 0x0);
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usleep_range(5, 10);
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reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
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FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) |
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FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase);
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mci_writel(host, UHS_REG_EXT, reg_value);
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mci_writel(host, ENABLE_SHIFT, enable_shift);
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reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |
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FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly);
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mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
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/* We should delay 1ms wait for timing setting finished. */
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usleep_range(1000, 2000);
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}
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static int dw_mci_hi3660_init(struct dw_mci *host)
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{
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mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
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SDMMC_CARD_RD_THR_EN));
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dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
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host->bus_hz /= (GENCLK_DIV + 1);
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return 0;
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}
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static int dw_mci_set_sel18(struct dw_mci *host, bool set)
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{
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int ret;
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unsigned int val;
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struct k3_priv *priv;
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priv = host->priv;
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val = set ? SDCARD_IO_SEL18 : 0;
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ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5,
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SDCARD_IO_SEL18, val);
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if (ret) {
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dev_err(host->dev, "sel18 %u error\n", val);
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return ret;
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}
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return 0;
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}
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static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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int ret;
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unsigned long wanted;
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unsigned long actual;
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struct k3_priv *priv = host->priv;
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if (!ios->clock || ios->clock == priv->cur_speed)
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return;
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wanted = ios->clock * (GENCLK_DIV + 1);
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ret = clk_set_rate(host->ciu_clk, wanted);
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if (ret) {
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dev_err(host->dev, "failed to set rate %luHz\n", wanted);
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return;
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}
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actual = clk_get_rate(host->ciu_clk);
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dw_mci_hs_set_timing(host, ios->timing, -1);
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host->bus_hz = actual / (GENCLK_DIV + 1);
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host->current_speed = 0;
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priv->cur_speed = host->bus_hz;
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}
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static int dw_mci_get_best_clksmpl(unsigned int sample_flag)
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{
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int i;
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int interval;
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unsigned int v;
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unsigned int len;
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unsigned int range_start = 0;
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unsigned int range_length = 0;
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unsigned int middle_range = 0;
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if (!sample_flag)
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return -EIO;
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if (~sample_flag == 0)
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return 0;
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i = ffs(sample_flag) - 1;
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/*
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* A clock cycle is divided into 32 phases,
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* each of which is represented by a bit,
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* finding the optimal phase.
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*/
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while (i < 32) {
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v = ror32(sample_flag, i);
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len = ffs(~v) - 1;
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if (len > range_length) {
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range_length = len;
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range_start = i;
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}
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interval = ffs(v >> len) - 1;
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if (interval < 0)
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break;
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i += len + interval;
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}
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middle_range = range_start + range_length / 2;
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if (middle_range >= 32)
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middle_range %= 32;
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return middle_range;
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}
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static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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{
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int i = 0;
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struct dw_mci *host = slot->host;
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struct mmc_host *mmc = slot->mmc;
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int smpl_phase = 0;
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u32 tuning_sample_flag = 0;
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int best_clksmpl = 0;
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for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
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smpl_phase %= 32;
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mci_writel(host, TMOUT, ~0);
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dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
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if (!mmc_send_tuning(mmc, opcode, NULL))
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tuning_sample_flag |= (1 << smpl_phase);
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else
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tuning_sample_flag &= ~(1 << smpl_phase);
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}
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best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag);
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if (best_clksmpl < 0) {
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dev_err(host->dev, "All phases bad!\n");
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return -EIO;
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}
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dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl);
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dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n",
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best_clksmpl, tuning_sample_flag);
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return 0;
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}
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static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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int ret = 0;
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struct dw_mci_slot *slot = mmc_priv(mmc);
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struct k3_priv *priv;
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struct dw_mci *host;
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host = slot->host;
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priv = host->priv;
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if (!priv || !priv->reg)
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return 0;
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if (priv->ctrl_id == DWMMC_SDIO_ID)
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return 0;
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
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ret = dw_mci_set_sel18(host, 0);
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else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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ret = dw_mci_set_sel18(host, 1);
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if (ret)
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return ret;
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if (!IS_ERR(mmc->supply.vqmmc)) {
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ret = mmc_regulator_set_vqmmc(mmc, ios);
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if (ret) {
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dev_err(host->dev, "Regulator set error %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static const struct dw_mci_drv_data hi3660_data = {
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.init = dw_mci_hi3660_init,
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.set_ios = dw_mci_hi3660_set_ios,
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.parse_dt = dw_mci_hi6220_parse_dt,
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.execute_tuning = dw_mci_hi3660_execute_tuning,
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.switch_voltage = dw_mci_hi3660_switch_voltage,
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};
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static const struct of_device_id dw_mci_k3_match[] = {
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{ .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, },
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{ .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
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{ .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
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{},
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@ -314,6 +314,8 @@ struct dw_mci_board {
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_CDTHRCTL 0x100
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#define SDMMC_UHS_REG_EXT 0x108
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#define SDMMC_ENABLE_SHIFT 0x110
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#define SDMMC_DATA(x) (x)
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/*
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* Registers to support idmac 64-bit address mode
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