drm/i915: clean up media reset on gm45
Originally I've thought that this fixes up the reset issues on my gm45, but that was just a red herring due to b0rked testing. Still I much prefer writing the right values (all other fields are reserved) instead of potentially dragging gunk around. Hence also clear the register to 0 after a reset. Note that Cspec is a bit confused and doesn't explicitly say that all the other bits in this register are "reserved, mbz" like usually. Instead they're marked as "r/o, default value = 0" which semantically amounts to the same thing. v2: Stop claiming this fixes anything and return 0 if successful instead of stack garbage. v3: Pimp the commit message to explain exactly why I think the docs allow us to ditch the rmw cycle, spurred by a discussion with Chris. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -798,28 +798,29 @@ static int i965_reset_complete(struct drm_device *dev)
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static int i965_do_reset(struct drm_device *dev)
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{
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int ret;
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u8 gdrst;
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/*
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* Set the domains we want to reset (GRDOM/bits 2 and 3) as
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* well as the reset bit (GR/bit 0). Setting the GR bit
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* triggers the reset; when done, the hardware will clear it.
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*/
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pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
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pci_write_config_byte(dev->pdev, I965_GDRST,
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gdrst | GRDOM_RENDER |
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GRDOM_RESET_ENABLE);
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GRDOM_RENDER | GRDOM_RESET_ENABLE);
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ret = wait_for(i965_reset_complete(dev), 500);
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if (ret)
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return ret;
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/* We can't reset render&media without also resetting display ... */
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pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
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pci_write_config_byte(dev->pdev, I965_GDRST,
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gdrst | GRDOM_MEDIA |
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GRDOM_RESET_ENABLE);
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GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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return wait_for(i965_reset_complete(dev), 500);
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ret = wait_for(i965_reset_complete(dev), 500);
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if (ret)
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return ret;
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pci_write_config_byte(dev->pdev, I965_GDRST, 0);
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return 0;
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}
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static int ironlake_do_reset(struct drm_device *dev)
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