[ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.
Mark page table walks with outer-cacheable attribute, and enable no-execute in page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -21,6 +21,14 @@
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#define D_CACHE_LINE_SIZE 32
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_IMP (1 << 2)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_WBWA (1 << 3)
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#define TTB_RGN_WT (2 << 3)
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#define TTB_RGN_WB (3 << 3)
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.macro cpsie, flags
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.ifc \flags, f
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.long 0xf1080040
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@ -115,7 +123,7 @@ ENTRY(cpu_v6_switch_mm)
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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#ifdef CONFIG_SMP
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orr r0, r0, #2 @ set shared pgtable
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orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
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#endif
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
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@ -161,8 +169,8 @@ ENTRY(cpu_v6_set_pte)
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tst r1, #L_PTE_YOUNG
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biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
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@ tst r1, #L_PTE_EXEC
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@ orreq r2, r2, #PTE_EXT_XN
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tst r1, #L_PTE_EXEC
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orreq r2, r2, #PTE_EXT_XN
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tst r1, #L_PTE_PRESENT
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moveq r2, #0
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@ -221,7 +229,7 @@ __v6_setup:
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mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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#ifdef CONFIG_SMP
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orr r4, r4, #2 @ set shared pgtable
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orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
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#endif
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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#ifdef CONFIG_VFP
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