V4L/DVB (11215): zl10353: add support for Intel CE6230 and Intel CE6231
Add chip IDs and configuration registers needed for Intel CE6230 and Intel CE6231. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -572,6 +572,10 @@ static int zl10353_init(struct dvb_frontend *fe)
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zl10353_dump_regs(fe);
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zl10353_dump_regs(fe);
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if (state->config.parallel_ts)
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if (state->config.parallel_ts)
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zl10353_reset_attach[2] &= ~0x20;
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zl10353_reset_attach[2] &= ~0x20;
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if (state->config.clock_ctl_1)
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zl10353_reset_attach[3] = state->config.clock_ctl_1;
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if (state->config.pll_0)
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zl10353_reset_attach[4] = state->config.pll_0;
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/* Do a "hard" reset if not already done */
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/* Do a "hard" reset if not already done */
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if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
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if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
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@ -614,6 +618,7 @@ struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
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struct i2c_adapter *i2c)
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struct i2c_adapter *i2c)
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{
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{
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struct zl10353_state *state = NULL;
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struct zl10353_state *state = NULL;
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int id;
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/* allocate memory for the internal state */
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/* allocate memory for the internal state */
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state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
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state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
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@ -625,7 +630,8 @@ struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
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memcpy(&state->config, config, sizeof(struct zl10353_config));
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memcpy(&state->config, config, sizeof(struct zl10353_config));
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/* check if the demod is there */
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/* check if the demod is there */
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if (zl10353_read_register(state, CHIP_ID) != ID_ZL10353)
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id = zl10353_read_register(state, CHIP_ID);
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if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
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goto error;
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goto error;
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/* create dvb_frontend */
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/* create dvb_frontend */
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@ -41,6 +41,10 @@ struct zl10353_config
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/* set if i2c_gate_ctrl disable is required */
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/* set if i2c_gate_ctrl disable is required */
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u8 disable_i2c_gate_ctrl:1;
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u8 disable_i2c_gate_ctrl:1;
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/* clock control registers (0x51-0x54) */
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u8 clock_ctl_1; /* default: 0x46 */
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u8 pll_0; /* default: 0x15 */
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};
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};
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#if defined(CONFIG_DVB_ZL10353) || (defined(CONFIG_DVB_ZL10353_MODULE) && defined(MODULE))
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#if defined(CONFIG_DVB_ZL10353) || (defined(CONFIG_DVB_ZL10353_MODULE) && defined(MODULE))
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@ -22,7 +22,9 @@
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#ifndef _ZL10353_PRIV_
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#ifndef _ZL10353_PRIV_
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#define _ZL10353_PRIV_
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#define _ZL10353_PRIV_
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#define ID_ZL10353 0x14
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#define ID_ZL10353 0x14 /* Zarlink ZL10353 */
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#define ID_CE6230 0x18 /* Intel CE6230 */
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#define ID_CE6231 0x19 /* Intel CE6231 */
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#define msb(x) (((x) >> 8) & 0xff)
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#define msb(x) (((x) >> 8) & 0xff)
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#define lsb(x) ((x) & 0xff)
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#define lsb(x) ((x) & 0xff)
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@ -50,6 +52,10 @@ enum zl10353_reg_addr {
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TPS_RECEIVED_0 = 0x1E,
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TPS_RECEIVED_0 = 0x1E,
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TPS_CURRENT_1 = 0x1F,
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TPS_CURRENT_1 = 0x1F,
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TPS_CURRENT_0 = 0x20,
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TPS_CURRENT_0 = 0x20,
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CLOCK_CTL_0 = 0x51,
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CLOCK_CTL_1 = 0x52,
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PLL_0 = 0x53,
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PLL_1 = 0x54,
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RESET = 0x55,
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RESET = 0x55,
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AGC_TARGET = 0x56,
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AGC_TARGET = 0x56,
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MCLK_RATIO = 0x5C,
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MCLK_RATIO = 0x5C,
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