Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner:
"A small set of fixes for x86:
- Prevent X2APIC ID 0xFFFFFFFF from being treated as valid, which
causes the possible CPU count to be wrong.
- Prevent 32bit truncation in calc_hpet_ref() which causes the TSC
calibration to fail
- Fix the page table setup for temporary text mappings in the resume
code which causes resume failures
- Make the page table dump code handle HIGHPTE correctly instead of
oopsing
- Support for topologies where NUMA nodes share an LLC to prevent a
invalid topology warning and further malfunction on such systems.
- Remove the now unused pci-nommu code
- Remove stale function declarations"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/power/64: Fix page-table setup for temporary text mapping
x86/mm: Prevent kernel Oops in PTDUMP code with HIGHPTE=y
x86,sched: Allow topologies where NUMA nodes share an LLC
x86/processor: Remove two unused function declarations
x86/acpi: Prevent X2APIC id 0xffffffff from being accounted
x86/tsc: Prevent 32bit truncation in calc_hpet_ref()
x86: Remove pci-nommu.c
hifive-unleashed-5.1
Linus Torvalds
commit
37a535edd7
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@ -749,13 +749,11 @@ enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
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extern void enable_sep_cpu(void);
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extern int sysenter_setup(void);
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extern void early_trap_init(void);
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void early_trap_pf_init(void);
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/* Defined in head.S */
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extern struct desc_ptr early_gdt_descr;
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extern void cpu_set_gdt(int);
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extern void switch_to_new_gdt(int);
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extern void load_direct_gdt(int);
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extern void load_fixmap_gdt(int);
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@ -215,6 +215,10 @@ acpi_parse_x2apic(struct acpi_subtable_header *header, const unsigned long end)
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apic_id = processor->local_apic_id;
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enabled = processor->lapic_flags & ACPI_MADT_ENABLED;
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/* Ignore invalid ID */
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if (apic_id == 0xffffffff)
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return 0;
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/*
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* We need to register disabled CPU as well to permit
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* counting disabled CPUs. This allows us to size
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@ -1,90 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Fallback functions when the main IOMMU code is not compiled in. This
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code is roughly equivalent to i386. */
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#include <linux/dma-direct.h>
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#include <linux/scatterlist.h>
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#include <linux/string.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/iommu.h>
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#include <asm/dma.h>
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#define NOMMU_MAPPING_ERROR 0
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static int
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check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
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{
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if (hwdev && !dma_capable(hwdev, bus, size)) {
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if (*hwdev->dma_mask >= DMA_BIT_MASK(32))
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printk(KERN_ERR
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"nommu_%s: overflow %Lx+%zu of device mask %Lx\n",
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name, (long long)bus, size,
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(long long)*hwdev->dma_mask);
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return 0;
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}
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return 1;
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}
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static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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dma_addr_t bus = phys_to_dma(dev, page_to_phys(page)) + offset;
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WARN_ON(size == 0);
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if (!check_addr("map_single", dev, bus, size))
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return NOMMU_MAPPING_ERROR;
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return bus;
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}
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/* Map a set of buffers described by scatterlist in streaming
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* mode for DMA. This is the scatter-gather version of the
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* above pci_map_single interface. Here the scatter gather list
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* elements are each tagged with the appropriate dma address
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* and length. They are obtained via sg_dma_{address,length}(SG).
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*
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* NOTE: An implementation may be able to use a smaller number of
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* DMA address/length pairs than there are SG table elements.
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* (for example via virtual mapping capabilities)
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* The routine returns the number of addr/length pairs actually
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* used, at most nents.
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*
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* Device ownership issues as mentioned above for pci_map_single are
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* the same here.
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*/
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static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct scatterlist *s;
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int i;
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WARN_ON(nents == 0 || sg[0].length == 0);
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for_each_sg(sg, s, nents, i) {
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BUG_ON(!sg_page(s));
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s->dma_address = sg_phys(s);
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if (!check_addr("map_sg", hwdev, s->dma_address, s->length))
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return 0;
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s->dma_length = s->length;
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}
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return nents;
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}
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static int nommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return dma_addr == NOMMU_MAPPING_ERROR;
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}
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const struct dma_map_ops nommu_dma_ops = {
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.alloc = dma_generic_alloc_coherent,
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.free = dma_generic_free_coherent,
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.map_sg = nommu_map_sg,
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.map_page = nommu_map_page,
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.is_phys = 1,
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.mapping_error = nommu_mapping_error,
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.dma_supported = x86_dma_supported,
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};
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@ -77,6 +77,8 @@
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#include <asm/i8259.h>
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#include <asm/misc.h>
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#include <asm/qspinlock.h>
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#include <asm/intel-family.h>
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#include <asm/cpu_device_id.h>
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/* Number of siblings per CPU package */
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int smp_num_siblings = 1;
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@ -390,15 +392,47 @@ static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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return false;
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}
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/*
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* Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
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*
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* These are Intel CPUs that enumerate an LLC that is shared by
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* multiple NUMA nodes. The LLC on these systems is shared for
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* off-package data access but private to the NUMA node (half
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* of the package) for on-package access.
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*
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* CPUID (the source of the information about the LLC) can only
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* enumerate the cache as being shared *or* unshared, but not
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* this particular configuration. The CPU in this case enumerates
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* the cache to be shared across the entire package (spanning both
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* NUMA nodes).
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*/
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static const struct x86_cpu_id snc_cpu[] = {
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{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
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{}
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};
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static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
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{
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int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
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if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
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per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
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return topology_sane(c, o, "llc");
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/* Do not match if we do not have a valid APICID for cpu: */
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if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
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return false;
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return false;
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/* Do not match if LLC id does not match: */
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if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
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return false;
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/*
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* Allow the SNC topology without warning. Return of false
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* means 'c' does not share the LLC of 'o'. This will be
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* reflected to userspace.
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*/
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if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
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return false;
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return topology_sane(c, o, "llc");
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}
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/*
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@ -456,7 +490,8 @@ static struct sched_domain_topology_level x86_topology[] = {
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/*
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* Set if a package/die has multiple NUMA nodes inside.
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* AMD Magny-Cours and Intel Cluster-on-Die have this.
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* AMD Magny-Cours, Intel Cluster-on-Die, and Intel
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* Sub-NUMA Clustering have this.
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*/
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static bool x86_has_numa_in_package;
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@ -317,7 +317,7 @@ static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
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hpet2 -= hpet1;
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tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
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do_div(tmp, 1000000);
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do_div(deltatsc, tmp);
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deltatsc = div64_u64(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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@ -18,6 +18,7 @@
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/highmem.h>
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#include <asm/pgtable.h>
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@ -334,16 +335,16 @@ static void walk_pte_level(struct seq_file *m, struct pg_state *st, pmd_t addr,
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pgprotval_t eff_in, unsigned long P)
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{
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int i;
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pte_t *start;
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pte_t *pte;
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pgprotval_t prot, eff;
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start = (pte_t *)pmd_page_vaddr(addr);
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for (i = 0; i < PTRS_PER_PTE; i++) {
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prot = pte_flags(*start);
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eff = effective_prot(eff_in, prot);
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st->current_address = normalize_addr(P + i * PTE_LEVEL_MULT);
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pte = pte_offset_map(&addr, st->current_address);
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prot = pte_flags(*pte);
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eff = effective_prot(eff_in, prot);
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note_page(m, st, __pgprot(prot), eff, 5);
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start++;
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pte_unmap(pte);
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}
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}
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#ifdef CONFIG_KASAN
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@ -98,7 +98,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
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set_pgd(pgd + pgd_index(restore_jump_address), new_pgd);
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} else {
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/* No p4d for 4-level paging: point the pgd to the pud page table */
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pgd_t new_pgd = __pgd(__pa(p4d) | pgprot_val(pgtable_prot));
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pgd_t new_pgd = __pgd(__pa(pud) | pgprot_val(pgtable_prot));
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set_pgd(pgd + pgd_index(restore_jump_address), new_pgd);
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}
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Loading…
Reference in New Issue