clk: tegra: Changes for v5.7-rc1
These changes remove PMC clocks from the clock and reset controller driver because they are controlled by bits in the PMC controller. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl5rs/8THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoRuvD/45ZRenGVCVxxvFqEgs7p2Vwpv8373P UQx8atoK61wb6F9+crGdLhOUBiT/hBOsDkbeR6Pgi3zLNEtVLM02SQUPQmux1qNG 5GD9QrRkLWF6k91ovwGNDErfwmHtUmGZd3sCADTQs5361A3Yj7UGpkYb7Sx9anxo MLbwTNepOhrfqqyVKy11wyWYXiuU71qZosT/Hvgg/TuXxwePrKaCmgry631X98vf 88NNDsT/P82nnsdBqZFMagxBlolzhCZSxkfwEcboHxxadCXhxa+RQkTkFFzbQwtd Grs2sG2nrSEczAAuzyOYGPwq75ZqCg3roqdfXBEeGcGAiLqjibUizu8EYp5rkydI FtGIQK9bHGUoa+4/wtlLiMfzLTRvjB0WbpG0fK53lSasyfHgatqMlu0yD3PF5tgc zcVicb3wVPhRi+1mn3gY+yZD99GHgtwGodbOp2kaKNgXajdUDH76xgXq/RDISF7n qPe41CQtlACeo1MQ61O42BPRMOSgtsE7XaJZh8PdtqxrsGn0PSkyvWnFH4r3w6RM /jmJNax1ak9oNFODP6i02wwv8XY03sRzWEeOrHcVWWh0YJeI1x9gxVwvDhpW3odp 4Z38LVK29ZbKRxO6KbsehqUiaqtJEfHcPoj+CLO6OIAK4suB5hzHNAInPzUNVWHi ED1ebh57Yej9Rg== =iXOG -----END PGP SIGNATURE----- Merge tag 'for-5.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra Pull Nvidia Tegra clk driver updates from Thierry Reding: These changes remove PMC clocks from the clock and reset controller driver because they are controlled by bits in the PMC controller. * tag 'for-5.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Remove audio clocks configuration from clock driver clk: tegra: Remove tegra_pmc_clk_init along with clk ids clk: tegra: Remove CLK_M_DIV fixed clocks clk: tegra: Fix Tegra PMC clock out parents clk: tegra: Add Tegra OSC to clock lookup clk: tegra: Add support for OSC_DIV fixed clocks dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks
This commit is contained in:
Stephen Boyd
commit
37a94882a3
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@ -1,300 +0,0 @@
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NVIDIA Tegra Power Management Controller (PMC)
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== Power Management Controller Node ==
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain one of the following:
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For Tegra20 must contain "nvidia,tegra20-pmc".
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For Tegra30 must contain "nvidia,tegra30-pmc".
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For Tegra114 must contain "nvidia,tegra114-pmc"
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For Tegra124 must contain "nvidia,tegra124-pmc"
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For Tegra132 must contain "nvidia,tegra124-pmc"
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For Tegra210 must contain "nvidia,tegra210-pmc"
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Hardware-triggered thermal reset:
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On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
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hardware-triggered thermal reset will be enabled.
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Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
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described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
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Tegra K1 Technical Reference Manual.
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- nvidia,bus-addr : Bus address of the PMU on the I2C bus
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- nvidia,reg-addr : I2C register address to write poweroff command to
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- nvidia,reg-data : Poweroff command to write to PMU
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Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Optional nodes:
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- powergates : This node contains a hierarchy of power domain nodes, which
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should match the powergates on the Tegra SoC. See "Powergate
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Nodes" below.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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pmc@7000f400 {
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i2c-thermtrip {
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nvidia,i2c-controller-id = <4>;
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nvidia,bus-addr = <0x40>;
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nvidia,reg-addr = <0x36>;
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nvidia,reg-data = <0x2>;
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};
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};
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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== Powergate Nodes ==
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Each of the powergate nodes represents a power-domain on the Tegra SoC
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that can be power-gated by the Tegra PMC. The name of the powergate node
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should be one of the below. Note that not every powergate is applicable
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to all Tegra devices and the following list shows which powergates are
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applicable to which devices. Please refer to the Tegra TRM for more
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details on the various powergates.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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Required properties:
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- clocks: Must contain an entry for each clock required by the PMC for
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controlling a power-gate. See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each reset required by the PMC for
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controlling a power-gate. See ../reset/reset.txt for details.
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- #power-domain-cells: Must be 0.
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Example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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powergates {
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pd_audio: aud {
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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resets = <&tegra_car 198>;
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#power-domain-cells = <0>;
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};
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};
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};
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== Powergate Clients ==
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Hardware blocks belonging to a power domain should contain a "power-domains"
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property that is a phandle pointing to the corresponding powergate node.
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Example:
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adma: adma@702e2000 {
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...
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power-domains = <&pd_audio>;
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...
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};
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== Pad Control ==
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On Tegra SoCs a pad is a set of pins which are configured as a group.
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The pin grouping is a fixed attribute of the hardware. The PMC can be
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used to set pad power state and signaling voltage. A pad can be either
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in active or power down mode. The support for power state and signaling
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voltage configuration varies depending on the pad in question. 3.3 V and
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1.8 V signaling voltages are supported on pins where software
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controllable signaling voltage switching is available.
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The pad configuration state nodes are placed under the pmc node and they
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are referred to by the pinctrl client properties. For more information
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see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
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The pad name should be used as the value of the pins property in pin
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configuration nodes.
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The following pads are present on Tegra124 and Tegra132:
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audio bb cam comp
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csia csb cse dsi
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dsib dsic dsid hdmi
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hsic hv lvds mipi-bias
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nand pex-bias pex-clk1 pex-clk2
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pex-cntrl sdmmc1 sdmmc3 sdmmc4
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sys_ddc uart usb0 usb1
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usb2 usb_bias
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The following pads are present on Tegra210:
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audio audio-hv cam csia
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csib csic csid csie
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csif dbg debug-nonao dmic
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dp dsi dsib dsic
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dsid emmc emmc2 gpio
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hdmi hsic lvds mipi-bias
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pex-bias pex-clk1 pex-clk2 pex-cntrl
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sdmmc1 sdmmc3 spi spi-hv
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uart usb0 usb1 usb2
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usb3 usb-bias
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Required pin configuration properties:
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- pins: Must contain name of the pad(s) to be configured.
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Optional pin configuration properties:
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- low-power-enable: Configure the pad into power down mode
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- low-power-disable: Configure the pad into active mode
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- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
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or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
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The values are defined in
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include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
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Note: The power state can be configured on all of the Tegra124 and
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Tegra132 pads. None of the Tegra124 or Tegra132 pads support
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signaling voltage switching.
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Note: All of the listed Tegra210 pads except pex-cntrl support power
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state configuration. Signaling voltage switching is supported on
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following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
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pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
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Pad configuration state example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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...
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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hdmi_off: hdmi-off {
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pins = "hdmi";
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low-power-enable;
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}
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hdmi_on: hdmi-on {
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pins = "hdmi";
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low-power-disable;
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}
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};
|
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||||
Pinctrl client example:
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sdmmc1: sdhci@700b0000 {
|
||||
...
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||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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};
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...
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sor@54540000 {
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||||
...
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||||
pinctrl-0 = <&hdmi_off>;
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pinctrl-1 = <&hdmi_on>;
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||||
pinctrl-names = "hdmi-on", "hdmi-off";
|
||||
};
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|
|
@ -0,0 +1,354 @@
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|||
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Tegra Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra30-pmc
|
||||
- nvidia,tegra114-pmc
|
||||
- nvidia,tegra124-pmc
|
||||
- nvidia,tegra210-pmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Offset and length of the register set for the device.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: clk32k_in
|
||||
description:
|
||||
Must includes entries pclk and clk32k_in.
|
||||
pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
|
||||
input to Tegra.
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description:
|
||||
Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clocks-bindings.txt for details.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
|
||||
PMC also has blink control which allows 32Khz clock output to
|
||||
Tegra blink pad.
|
||||
Consumer of PMC clock should specify the desired clock by having
|
||||
the clock ID in its "clocks" phandle cell with pmc clock provider.
|
||||
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
|
||||
clock IDs.
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
description:
|
||||
Specifies number of cells needed to encode an interrupt source.
|
||||
The value must be 2.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
nvidia,invert-interrupt:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and
|
||||
then fed into the ARM GIC. The PMC is not involved in the detection
|
||||
or handling of this interrupt signal, merely its inversion.
|
||||
|
||||
nvidia,core-power-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Core power request active-high.
|
||||
|
||||
nvidia,sys-clock-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: System clock request active-high.
|
||||
|
||||
nvidia,combined-power-req:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: combined power request for CPU and Core.
|
||||
|
||||
nvidia,cpu-pwr-good-en:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
CPU power good signal from external PMIC to PMC is enabled.
|
||||
|
||||
nvidia,suspend-mode:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2]
|
||||
description:
|
||||
The suspend mode that the platform should use.
|
||||
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
|
||||
Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
|
||||
Mode 2 is for LP2, CPU voltage off
|
||||
|
||||
nvidia,cpu-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power good time in uSec.
|
||||
|
||||
nvidia,cpu-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power off time in uSec.
|
||||
|
||||
nvidia,core-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uSec.
|
||||
|
||||
nvidia,core-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Core power off time in uSec.
|
||||
|
||||
nvidia,lp0-vec:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<start length> Starting address and length of LP0 vector.
|
||||
The LP0 vector contains the warm boot code that is executed
|
||||
by AVP when resuming from the LP0 state.
|
||||
The AVP (Audio-Video Processor) is an ARM7 processor and
|
||||
always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed
|
||||
from the deep sleep mode, the warm boot code will restore
|
||||
some PLLs, clocks and then brings up CPU0 for resuming the
|
||||
system.
|
||||
|
||||
i2c-thermtrip:
|
||||
type: object
|
||||
description:
|
||||
On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
|
||||
hardware-triggered thermal reset will be enabled.
|
||||
|
||||
properties:
|
||||
nvidia,i2c-controller-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
ID of I2C controller to send poweroff command to PMU.
|
||||
Valid values are described in section 9.2.148
|
||||
"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
|
||||
Manual.
|
||||
|
||||
nvidia,bus-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Bus address of the PMU on the I2C bus.
|
||||
|
||||
nvidia,reg-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: PMU I2C register address to issue poweroff command.
|
||||
|
||||
nvidia,reg-data:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Poweroff command to write to PMU.
|
||||
|
||||
nvidia,pinmux-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Pinmux used by the hardware when issuing Poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
required:
|
||||
- nvidia,i2c-controller-id
|
||||
- nvidia,bus-addr
|
||||
- nvidia,reg-addr
|
||||
- nvidia,reg-data
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
powergates:
|
||||
type: object
|
||||
description: |
|
||||
This node contains a hierarchy of power domain nodes, which should
|
||||
match the powergates on the Tegra SoC. Each powergate node
|
||||
represents a power-domain on the Tegra SoC that can be power-gated
|
||||
by the Tegra PMC.
|
||||
Hardware blocks belonging to a power domain should contain
|
||||
"power-domains" property that is a phandle pointing to corresponding
|
||||
powergate node.
|
||||
The name of the powergate node should be one of the below. Note that
|
||||
not every powergate is applicable to all Tegra devices and the following
|
||||
list shows which powergates are applicable to which devices.
|
||||
Please refer to Tegra TRM for mode details on the powergate nodes to
|
||||
use for each power-gate block inside Tegra.
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+$":
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each clock required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../clocks/clock-bindings.txt document for more details.
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each reset required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../reset/reset.txt for more details.
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
description: Must be 0.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- resets
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"^[a-f0-9]+-[a-f0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
This is a Pad configuration node. On Tegra SOCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power state
|
||||
and signaling voltage. A pad can be either in active or power down mode.
|
||||
The support for power state and signaling voltage configuration varies
|
||||
depending on the pad in question. 3.3V and 1.8V signaling voltages
|
||||
are supported on pins where software controllable signaling voltage
|
||||
switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132
|
||||
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
|
||||
hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
|
||||
sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
|
||||
|
||||
The following pads are present on Tegra210
|
||||
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
|
||||
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
|
||||
hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain name of the pad(s) to be configured.
|
||||
|
||||
low-power-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into power down mode.
|
||||
|
||||
low-power-disable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into active mode.
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
Power state can be configured on all Tegra124 and Tegra132
|
||||
pads. None of the Tegra124 or Tegra132 pads support signaling
|
||||
voltage switching.
|
||||
All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported
|
||||
on below Tegra210 pads.
|
||||
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
dependencies:
|
||||
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
|
||||
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
|
||||
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/soc/tegra-pmc.h>
|
||||
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -12,7 +12,6 @@ obj-y += clk-sdmmc-mux.o
|
|||
obj-y += clk-super.o
|
||||
obj-y += clk-tegra-audio.o
|
||||
obj-y += clk-tegra-periph.o
|
||||
obj-y += clk-tegra-pmc.o
|
||||
obj-y += clk-tegra-fixed.o
|
||||
obj-y += clk-tegra-super-gen4.o
|
||||
obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@ enum clk_id {
|
|||
tegra_clk_audio4,
|
||||
tegra_clk_audio4_2x,
|
||||
tegra_clk_audio4_mux,
|
||||
tegra_clk_blink,
|
||||
tegra_clk_bsea,
|
||||
tegra_clk_bsev,
|
||||
tegra_clk_cclk_g,
|
||||
|
|
@ -44,14 +43,9 @@ enum clk_id {
|
|||
tegra_clk_clk72Mhz,
|
||||
tegra_clk_clk72Mhz_8,
|
||||
tegra_clk_clk_m,
|
||||
tegra_clk_clk_m_div2,
|
||||
tegra_clk_clk_m_div4,
|
||||
tegra_clk_clk_out_1,
|
||||
tegra_clk_clk_out_1_mux,
|
||||
tegra_clk_clk_out_2,
|
||||
tegra_clk_clk_out_2_mux,
|
||||
tegra_clk_clk_out_3,
|
||||
tegra_clk_clk_out_3_mux,
|
||||
tegra_clk_osc,
|
||||
tegra_clk_osc_div2,
|
||||
tegra_clk_osc_div4,
|
||||
tegra_clk_cml0,
|
||||
tegra_clk_cml1,
|
||||
tegra_clk_csi,
|
||||
|
|
|
|||
|
|
@ -46,7 +46,28 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
|
||||
if (!dt_clk)
|
||||
return 0;
|
||||
|
||||
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
|
||||
*dt_clk = osc;
|
||||
|
||||
/* osc_div2 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
|
||||
0, 1, 2);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* osc_div4 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
|
||||
0, 1, 4);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
|
||||
if (!dt_clk)
|
||||
|
|
@ -84,22 +105,6 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
|
|||
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* clk_m_div2 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* clk_m_div4 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 4);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_clk_osc_resume(void __iomem *clk_base)
|
||||
|
|
|
|||
|
|
@ -1,122 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-id.h"
|
||||
|
||||
#define PMC_CLK_OUT_CNTRL 0x1a8
|
||||
#define PMC_DPD_PADS_ORIDE 0x1c
|
||||
#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
|
||||
#define PMC_CTRL 0
|
||||
#define PMC_CTRL_BLINK_ENB 7
|
||||
#define PMC_BLINK_TIMER 0x40
|
||||
|
||||
struct pmc_clk_init_data {
|
||||
char *mux_name;
|
||||
char *gate_name;
|
||||
const char **parents;
|
||||
int num_parents;
|
||||
int mux_id;
|
||||
int gate_id;
|
||||
char *dev_name;
|
||||
u8 mux_shift;
|
||||
u8 gate_shift;
|
||||
};
|
||||
|
||||
#define PMC_CLK(_num, _mux_shift, _gate_shift)\
|
||||
{\
|
||||
.mux_name = "clk_out_" #_num "_mux",\
|
||||
.gate_name = "clk_out_" #_num,\
|
||||
.parents = clk_out ##_num ##_parents,\
|
||||
.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
|
||||
.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
|
||||
.gate_id = tegra_clk_clk_out_ ##_num,\
|
||||
.dev_name = "extern" #_num,\
|
||||
.mux_shift = _mux_shift,\
|
||||
.gate_shift = _gate_shift,\
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(clk_out_lock);
|
||||
|
||||
static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
|
||||
"clk_m_div4", "extern1",
|
||||
};
|
||||
|
||||
static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
|
||||
"clk_m_div4", "extern2",
|
||||
};
|
||||
|
||||
static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
|
||||
"clk_m_div4", "extern3",
|
||||
};
|
||||
|
||||
static struct pmc_clk_init_data pmc_clks[] = {
|
||||
PMC_CLK(1, 6, 2),
|
||||
PMC_CLK(2, 14, 10),
|
||||
PMC_CLK(3, 22, 18),
|
||||
};
|
||||
|
||||
void __init tegra_pmc_clk_init(void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
|
||||
struct pmc_clk_init_data *data;
|
||||
|
||||
data = pmc_clks + i;
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = clk_register_mux(NULL, data->mux_name, data->parents,
|
||||
data->num_parents,
|
||||
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
|
||||
pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
|
||||
3, 0, &clk_out_lock);
|
||||
*dt_clk = clk;
|
||||
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
|
||||
CLK_SET_RATE_PARENT,
|
||||
pmc_base + PMC_CLK_OUT_CNTRL,
|
||||
data->gate_shift, 0, &clk_out_lock);
|
||||
*dt_clk = clk;
|
||||
clk_register_clkdev(clk, data->dev_name, data->gate_name);
|
||||
}
|
||||
|
||||
/* blink */
|
||||
writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
|
||||
clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
|
||||
pmc_base + PMC_DPD_PADS_ORIDE,
|
||||
PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
|
||||
if (!dt_clk)
|
||||
return;
|
||||
|
||||
clk = clk_register_gate(NULL, "blink", "blink_override", 0,
|
||||
pmc_base + PMC_CTRL,
|
||||
PMC_CTRL_BLINK_ENB, 0, NULL);
|
||||
clk_register_clkdev(clk, "blink", NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
|
|
@ -735,8 +735,9 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
|
||||
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
|
||||
|
|
@ -778,10 +779,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
|
||||
[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
|
||||
[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
|
||||
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
|
||||
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
|
||||
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
|
||||
|
|
@ -803,9 +800,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
|
||||
[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
|
||||
[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
|
||||
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
|
||||
[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
|
||||
|
|
@ -815,8 +809,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
|
||||
|
|
@ -863,10 +858,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
|
||||
{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
|
||||
|
|
@ -900,17 +894,6 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
|
|||
/* clk_32k */
|
||||
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
|
||||
clks[TEGRA114_CLK_CLK_32K] = clk;
|
||||
|
||||
/* clk_m_div2 */
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
|
||||
|
||||
/* clk_m_div4 */
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 4);
|
||||
clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
|
||||
|
||||
}
|
||||
|
||||
static void __init tegra114_pll_init(void __iomem *clk_base,
|
||||
|
|
@ -1153,11 +1136,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
|
@ -1359,7 +1339,6 @@ static void __init tegra114_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
|
||||
tegra114_audio_plls,
|
||||
ARRAY_SIZE(tegra114_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra114_clks);
|
||||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
|
||||
&pll_x_params);
|
||||
|
||||
|
|
|
|||
|
|
@ -860,8 +860,9 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
|
||||
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
|
||||
|
|
@ -902,10 +903,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
|
||||
[tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
|
||||
[tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
|
||||
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
|
||||
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
|
||||
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
|
||||
|
|
@ -931,9 +928,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
|
||||
[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
|
||||
[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
|
||||
};
|
||||
|
||||
|
|
@ -941,8 +935,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
|
||||
|
|
@ -988,10 +983,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
|
||||
{ .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
|
||||
|
|
@ -1298,11 +1292,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
|
|||
{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
|
@ -1457,11 +1448,9 @@ static void __init tegra132_clock_apply_init_table(void)
|
|||
* tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most of the clocks controlled by the CAR IP block, along
|
||||
* with a few clocks controlled by the PMC IP block. Everything in
|
||||
* this function should be common to Tegra124 and Tegra132. XXX The
|
||||
* PMC clock initialization should probably be moved to PMC-specific
|
||||
* driver code. No return value.
|
||||
* Register most of the clocks controlled by the CAR IP block.
|
||||
* Everything in this function should be common to Tegra124 and Tegra132.
|
||||
* No return value.
|
||||
*/
|
||||
static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
||||
{
|
||||
|
|
@ -1504,7 +1493,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
|
||||
tegra124_audio_plls,
|
||||
ARRAY_SIZE(tegra124_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra124_clks);
|
||||
|
||||
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
|
||||
plld_base = readl(clk_base + PLLD_BASE);
|
||||
|
|
@ -1516,11 +1504,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
|||
* tegra124_132_clock_init_post - clock initialization postamble for T124/T132
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most of the along with a few clocks controlled by the PMC
|
||||
* IP block. Everything in this function should be common to Tegra124
|
||||
* Register most of the clocks controlled by the CAR IP block.
|
||||
* Everything in this function should be common to Tegra124
|
||||
* and Tegra132. This function must be called after
|
||||
* tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
|
||||
* not be set. No return value.
|
||||
* tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
|
||||
* No return value.
|
||||
*/
|
||||
static void __init tegra124_132_clock_init_post(struct device_node *np)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
|
||||
{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
|
||||
{ .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
|
||||
{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
|
||||
{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
|
||||
|
|
@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
|
||||
[tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
|
||||
[tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
|
||||
[tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
|
||||
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
|
||||
|
|
@ -1031,10 +1029,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
|
||||
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
|
||||
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
|
||||
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
|
|
@ -1146,7 +1142,6 @@ static void __init tegra20_clock_init(struct device_node *np)
|
|||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
|
||||
tegra20_periph_clk_init();
|
||||
tegra20_audio_clk_init();
|
||||
tegra_pmc_clk_init(pmc_base, tegra20_clks);
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
|
||||
|
||||
|
|
|
|||
|
|
@ -2371,8 +2371,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
|
||||
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
|
||||
|
|
@ -2417,10 +2418,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
|
||||
[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
|
||||
[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
|
||||
[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
|
||||
[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
|
||||
[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
|
||||
|
|
@ -2452,9 +2449,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
|
||||
[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
|
||||
[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
|
||||
[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
|
||||
[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
|
||||
|
|
@ -2497,8 +2491,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
|
||||
|
|
@ -2540,10 +2535,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
|
||||
{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
|
||||
|
|
@ -3448,11 +3442,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
|
@ -3693,7 +3684,6 @@ static void __init tegra210_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
|
||||
tegra210_audio_plls,
|
||||
ARRAY_SIZE(tegra210_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra210_clks);
|
||||
|
||||
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
|
||||
value = readl(clk_base + PLLD_BASE);
|
||||
|
|
|
|||
|
|
@ -569,10 +569,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
|
||||
{ .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
|
||||
|
|
@ -581,8 +580,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
|
||||
{ .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
|
||||
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
|
||||
{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
|
||||
{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
|
||||
|
|
@ -683,8 +683,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
|
||||
[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
|
||||
|
|
@ -711,13 +712,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
|
||||
[tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
|
||||
[tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
|
||||
[tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
|
||||
[tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
|
||||
|
|
@ -1227,12 +1221,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
|
@ -1362,7 +1352,6 @@ static void __init tegra30_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
|
||||
tegra30_audio_plls,
|
||||
ARRAY_SIZE(tegra30_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra30_clks);
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
|
||||
|
||||
|
|
|
|||
|
|
@ -854,7 +854,6 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
|
|||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params);
|
||||
|
||||
void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
|
||||
void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
|
||||
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
|
||||
unsigned long *input_freqs, unsigned int num,
|
||||
|
|
|
|||
|
|
@ -228,6 +228,8 @@
|
|||
#define TEGRA114_CLK_CLK_M 201
|
||||
#define TEGRA114_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA114_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA114_CLK_OSC_DIV2 202
|
||||
#define TEGRA114_CLK_OSC_DIV4 203
|
||||
#define TEGRA114_CLK_PLL_REF 204
|
||||
#define TEGRA114_CLK_PLL_C 205
|
||||
#define TEGRA114_CLK_PLL_C_OUT1 206
|
||||
|
|
@ -274,7 +276,7 @@
|
|||
#define TEGRA114_CLK_CLK_OUT_2 246
|
||||
#define TEGRA114_CLK_CLK_OUT_3 247
|
||||
#define TEGRA114_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA114_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA114_CLK_XUSB_HOST_SRC 252
|
||||
|
|
|
|||
|
|
@ -227,6 +227,8 @@
|
|||
#define TEGRA124_CLK_CLK_M 201
|
||||
#define TEGRA124_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA124_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA124_CLK_OSC_DIV2 202
|
||||
#define TEGRA124_CLK_OSC_DIV4 203
|
||||
#define TEGRA124_CLK_PLL_REF 204
|
||||
#define TEGRA124_CLK_PLL_C 205
|
||||
#define TEGRA124_CLK_PLL_C_OUT1 206
|
||||
|
|
@ -273,7 +275,7 @@
|
|||
#define TEGRA124_CLK_CLK_OUT_2 246
|
||||
#define TEGRA124_CLK_CLK_OUT_3 247
|
||||
#define TEGRA124_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA124_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA124_CLK_XUSB_HOST_SRC 252
|
||||
|
|
|
|||
|
|
@ -262,6 +262,8 @@
|
|||
#define TEGRA210_CLK_CLK_M 233
|
||||
#define TEGRA210_CLK_CLK_M_DIV2 234
|
||||
#define TEGRA210_CLK_CLK_M_DIV4 235
|
||||
#define TEGRA210_CLK_OSC_DIV2 234
|
||||
#define TEGRA210_CLK_OSC_DIV4 235
|
||||
#define TEGRA210_CLK_PLL_REF 236
|
||||
#define TEGRA210_CLK_PLL_C 237
|
||||
#define TEGRA210_CLK_PLL_C_OUT1 238
|
||||
|
|
@ -355,7 +357,7 @@
|
|||
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
|
||||
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
|
||||
/* 325 */
|
||||
/* 326 */
|
||||
#define TEGRA210_CLK_OSC 326
|
||||
/* 327 */
|
||||
/* 328 */
|
||||
/* 329 */
|
||||
|
|
|
|||
|
|
@ -196,6 +196,8 @@
|
|||
#define TEGRA30_CLK_CLK_M 171
|
||||
#define TEGRA30_CLK_CLK_M_DIV2 172
|
||||
#define TEGRA30_CLK_CLK_M_DIV4 173
|
||||
#define TEGRA30_CLK_OSC_DIV2 172
|
||||
#define TEGRA30_CLK_OSC_DIV4 173
|
||||
#define TEGRA30_CLK_PLL_REF 174
|
||||
#define TEGRA30_CLK_PLL_C 175
|
||||
#define TEGRA30_CLK_PLL_C_OUT1 176
|
||||
|
|
@ -243,7 +245,7 @@
|
|||
#define TEGRA30_CLK_HCLK 217
|
||||
#define TEGRA30_CLK_PCLK 218
|
||||
/* 219 */
|
||||
/* 220 */
|
||||
#define TEGRA30_CLK_OSC 220
|
||||
/* 221 */
|
||||
/* 222 */
|
||||
/* 223 */
|
||||
|
|
|
|||
16
include/dt-bindings/soc/tegra-pmc.h
Normal file
16
include/dt-bindings/soc/tegra-pmc.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
|
||||
#define _DT_BINDINGS_SOC_TEGRA_PMC_H
|
||||
|
||||
#define TEGRA_PMC_CLK_OUT_1 0
|
||||
#define TEGRA_PMC_CLK_OUT_2 1
|
||||
#define TEGRA_PMC_CLK_OUT_3 2
|
||||
#define TEGRA_PMC_CLK_BLINK 3
|
||||
|
||||
#define TEGRA_PMC_CLK_MAX 4
|
||||
|
||||
#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
|
||||
Loading…
Reference in a new issue