drm/armada: split out primary plane update
Split out the primary plane update from the mode setting. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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8be523db65
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37af35c778
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@ -527,6 +527,34 @@ static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
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return val;
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}
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static void armada_drm_primary_set(struct drm_crtc *crtc,
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struct drm_plane *plane, int x, int y)
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{
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struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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struct armada_regs regs[7];
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bool interlaced = dcrtc->interlaced;
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unsigned i;
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uint32_t ctrl0;
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i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced);
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armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
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armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
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ctrl0 = state->ctrl0;
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if (interlaced)
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ctrl0 |= CFG_GRA_FTOGGLE;
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armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
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CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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CFG_SWAPYU | CFG_YUV2RGB) |
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CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
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LCD_SPU_DMA_CTRL0);
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armada_reg_queue_end(regs, i);
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armada_drm_crtc_update_regs(dcrtc, regs);
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}
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/* The mode_config.mutex will be held for this call */
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static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode, struct drm_display_mode *adj,
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@ -553,12 +581,10 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
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drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
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drm_to_armada_plane(crtc->primary)->state.src_hw =
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drm_to_armada_plane(crtc->primary)->state.dst_hw =
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adj->crtc_hdisplay << 16 | adj->crtc_vdisplay;
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adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
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drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
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i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
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x, y, regs, interlaced);
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i = 0;
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rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
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lm = adj->crtc_htotal - adj->crtc_hsync_end;
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bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
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@ -634,12 +660,6 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
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val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
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armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
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armada_reg_queue_set(regs, i,
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drm_to_armada_plane(crtc->primary)->state.src_hw,
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LCD_SPU_GRA_HPXL_VLN);
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armada_reg_queue_set(regs, i,
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drm_to_armada_plane(crtc->primary)->state.dst_hw,
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LCD_SPU_GZM_HPXL_VLN);
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armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
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armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
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armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
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@ -651,16 +671,6 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
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ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
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}
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val = drm_to_armada_plane(crtc->primary)->state.ctrl0;
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if (interlaced)
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val |= CFG_GRA_FTOGGLE;
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armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
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CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
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CFG_SWAPYU | CFG_YUV2RGB) |
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CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
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LCD_SPU_DMA_CTRL0);
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val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
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armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
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@ -669,6 +679,8 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
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armada_reg_queue_end(regs, i);
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armada_drm_crtc_update_regs(dcrtc, regs);
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armada_drm_primary_set(crtc, crtc->primary, x, y);
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spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
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armada_drm_crtc_update(dcrtc);
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