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MLK-21960-4: arm64: dts: enable fspi in imx8qxp dts 

enable fspi in imx8qxp DT file

Signed-off-by: Han Xu <han.xu@nxp.com>
[ Aisheng: sort in reg address and fix conflict ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Han Xu 2019-06-05 22:52:29 -05:00 committed by Dong Aisheng
parent f5fc8e4f9a
commit 37f783cdf8
2 changed files with 53 additions and 1 deletions
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17
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View File

@ -8,7 +8,8 @@ lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
<0x08000000 0x0 0x08000000 0x10000000>;
lsio_gpio0: gpio@5d080000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
@ -98,6 +99,20 @@ lsio_subsys: bus@5d000000 {
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
flexspi0: spi@5d120000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,imx8qxp-fspi";
reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX_LSIO_FSPI0_CLK>,
<&clk IMX_LSIO_FSPI0_CLK>;
clock-names = "fspi", "fspi_en";
power-domains = <&pd IMX_SC_R_FSPI_0>;
status = "disabled";
};
lsio_mu0: mailbox@5d1b0000 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>;

37
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -460,6 +460,22 @@
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&adma_i2c1 {
#address-cells = <1>;
#size-cells = <0>;
@ -788,6 +804,27 @@
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
pinctrl_ioexp_rst: ioexp_rst_grp {
fsl,pins = <
IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021