crypto: qat - Intel(R) QAT FW interface
This patch adds FW interface structure definitions. Acked-by: John Griffin <john.griffin@intel.com> Reviewed-by: Bruce W. Allan <bruce.w.allan@intel.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>hifive-unleashed-5.1
Tadeusz Struk
Herbert Xu
parent
a672a9dc87
commit
38154e65ce
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/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ICP_QAT_FW_H_
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#define _ICP_QAT_FW_H_
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#include <linux/types.h>
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#include "icp_qat_hw.h"
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#define QAT_FIELD_SET(flags, val, bitpos, mask) \
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{ (flags) = (((flags) & (~((mask) << (bitpos)))) | \
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(((val) & (mask)) << (bitpos))) ; }
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#define QAT_FIELD_GET(flags, bitpos, mask) \
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(((flags) >> (bitpos)) & (mask))
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#define ICP_QAT_FW_REQ_DEFAULT_SZ 128
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#define ICP_QAT_FW_RESP_DEFAULT_SZ 32
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#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
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#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
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#define ICP_QAT_FW_NUM_LONGWORDS_1 1
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#define ICP_QAT_FW_NUM_LONGWORDS_2 2
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#define ICP_QAT_FW_NUM_LONGWORDS_3 3
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#define ICP_QAT_FW_NUM_LONGWORDS_4 4
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#define ICP_QAT_FW_NUM_LONGWORDS_5 5
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#define ICP_QAT_FW_NUM_LONGWORDS_6 6
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#define ICP_QAT_FW_NUM_LONGWORDS_7 7
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#define ICP_QAT_FW_NUM_LONGWORDS_10 10
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#define ICP_QAT_FW_NUM_LONGWORDS_13 13
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#define ICP_QAT_FW_NULL_REQ_SERV_ID 1
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enum icp_qat_fw_comn_resp_serv_id {
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ICP_QAT_FW_COMN_RESP_SERV_NULL,
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ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
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ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
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};
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enum icp_qat_fw_comn_request_id {
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ICP_QAT_FW_COMN_REQ_NULL = 0,
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ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
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ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
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ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
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ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
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ICP_QAT_FW_COMN_REQ_DELIMITER
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};
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struct icp_qat_fw_comn_req_hdr_cd_pars {
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union {
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struct {
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uint64_t content_desc_addr;
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uint16_t content_desc_resrvd1;
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uint8_t content_desc_params_sz;
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uint8_t content_desc_hdr_resrvd2;
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uint32_t content_desc_resrvd3;
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} s;
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struct {
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uint32_t serv_specif_fields[4];
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} s1;
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} u;
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};
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struct icp_qat_fw_comn_req_mid {
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uint64_t opaque_data;
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uint64_t src_data_addr;
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uint64_t dest_data_addr;
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uint32_t src_length;
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uint32_t dst_length;
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};
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struct icp_qat_fw_comn_req_cd_ctrl {
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uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
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};
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struct icp_qat_fw_comn_req_hdr {
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uint8_t resrvd1;
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uint8_t service_cmd_id;
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uint8_t service_type;
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uint8_t hdr_flags;
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uint16_t serv_specif_flags;
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uint16_t comn_req_flags;
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};
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struct icp_qat_fw_comn_req_rqpars {
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uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
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};
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struct icp_qat_fw_comn_req {
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struct icp_qat_fw_comn_req_hdr comn_hdr;
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struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
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struct icp_qat_fw_comn_req_mid comn_mid;
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struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
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struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
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};
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struct icp_qat_fw_comn_error {
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uint8_t xlat_err_code;
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uint8_t cmp_err_code;
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};
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struct icp_qat_fw_comn_resp_hdr {
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uint8_t resrvd1;
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uint8_t service_id;
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uint8_t response_type;
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uint8_t hdr_flags;
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struct icp_qat_fw_comn_error comn_error;
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uint8_t comn_status;
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uint8_t cmd_id;
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};
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struct icp_qat_fw_comn_resp {
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struct icp_qat_fw_comn_resp_hdr comn_hdr;
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uint64_t opaque_data;
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uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
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};
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#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
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#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
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#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
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#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
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#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
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#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
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icp_qat_fw_comn_req_hdr_t.service_type
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#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
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icp_qat_fw_comn_req_hdr_t.service_type = val
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#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
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icp_qat_fw_comn_req_hdr_t.service_cmd_id
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#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
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icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
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#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
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ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
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#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
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ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
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#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
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QAT_FIELD_GET(hdr_flags, \
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ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
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ICP_QAT_FW_COMN_VALID_FLAG_MASK)
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#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
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(hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
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#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
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QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
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ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
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ICP_QAT_FW_COMN_VALID_FLAG_MASK)
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#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
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(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
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ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
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#define QAT_COMN_PTR_TYPE_BITPOS 0
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#define QAT_COMN_PTR_TYPE_MASK 0x1
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#define QAT_COMN_CD_FLD_TYPE_BITPOS 1
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#define QAT_COMN_CD_FLD_TYPE_MASK 0x1
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#define QAT_COMN_PTR_TYPE_FLAT 0x0
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#define QAT_COMN_PTR_TYPE_SGL 0x1
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#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
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#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
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#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
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((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
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| (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
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#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
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QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
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#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
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QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
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QAT_COMN_CD_FLD_TYPE_MASK)
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#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
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QAT_COMN_PTR_TYPE_MASK)
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#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
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QAT_COMN_CD_FLD_TYPE_MASK)
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#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
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#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
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#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
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#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
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#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
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((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
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>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
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#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
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{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
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& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
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((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
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& ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
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#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
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(((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
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#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
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{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
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& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
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((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
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#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
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#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
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#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
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#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
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#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
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#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
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#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
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#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
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#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
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((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
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QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
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(((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
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QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
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(((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
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QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
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(((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
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QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
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#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
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QAT_COMN_RESP_CRYPTO_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
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QAT_COMN_RESP_CMP_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
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QAT_COMN_RESP_XLAT_STATUS_MASK)
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#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
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QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
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QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
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#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
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#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
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#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
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#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
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#define ERR_CODE_NO_ERROR 0
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#define ERR_CODE_INVALID_BLOCK_TYPE -1
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#define ERR_CODE_NO_MATCH_ONES_COMP -2
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#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
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#define ERR_CODE_INCOMPLETE_LEN -4
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#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
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#define ERR_CODE_RPT_GT_SPEC_LEN -6
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#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
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#define ERR_CODE_INV_DIS_CODE_LEN -8
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#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
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#define ERR_CODE_DIS_TOO_FAR_BACK -10
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#define ERR_CODE_OVERFLOW_ERROR -11
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#define ERR_CODE_SOFT_ERROR -12
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#define ERR_CODE_FATAL_ERROR -13
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#define ERR_CODE_SSM_ERROR -14
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#define ERR_CODE_ENDPOINT_ERROR -15
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enum icp_qat_fw_slice {
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ICP_QAT_FW_SLICE_NULL = 0,
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ICP_QAT_FW_SLICE_CIPHER = 1,
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ICP_QAT_FW_SLICE_AUTH = 2,
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ICP_QAT_FW_SLICE_DRAM_RD = 3,
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ICP_QAT_FW_SLICE_DRAM_WR = 4,
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ICP_QAT_FW_SLICE_COMP = 5,
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ICP_QAT_FW_SLICE_XLAT = 6,
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ICP_QAT_FW_SLICE_DELIMITER
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};
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#endif
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@ -0,0 +1,131 @@
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/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _ICP_QAT_FW_INIT_ADMIN_H_
|
||||
#define _ICP_QAT_FW_INIT_ADMIN_H_
|
||||
|
||||
#include "icp_qat_fw.h"
|
||||
|
||||
enum icp_qat_fw_init_admin_cmd_id {
|
||||
ICP_QAT_FW_INIT_ME = 0,
|
||||
ICP_QAT_FW_TRNG_ENABLE = 1,
|
||||
ICP_QAT_FW_TRNG_DISABLE = 2,
|
||||
ICP_QAT_FW_CONSTANTS_CFG = 3,
|
||||
ICP_QAT_FW_STATUS_GET = 4,
|
||||
ICP_QAT_FW_COUNTERS_GET = 5,
|
||||
ICP_QAT_FW_LOOPBACK = 6,
|
||||
ICP_QAT_FW_HEARTBEAT_SYNC = 7,
|
||||
ICP_QAT_FW_HEARTBEAT_GET = 8
|
||||
};
|
||||
|
||||
enum icp_qat_fw_init_admin_resp_status {
|
||||
ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
|
||||
ICP_QAT_FW_INIT_RESP_STATUS_FAIL
|
||||
};
|
||||
|
||||
struct icp_qat_fw_init_admin_req {
|
||||
uint16_t init_cfg_sz;
|
||||
uint8_t resrvd1;
|
||||
uint8_t init_admin_cmd_id;
|
||||
uint32_t resrvd2;
|
||||
uint64_t opaque_data;
|
||||
uint64_t init_cfg_ptr;
|
||||
uint64_t resrvd3;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_init_admin_resp_hdr {
|
||||
uint8_t flags;
|
||||
uint8_t resrvd1;
|
||||
uint8_t status;
|
||||
uint8_t init_admin_cmd_id;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_init_admin_resp_pars {
|
||||
union {
|
||||
uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_4];
|
||||
struct {
|
||||
uint32_t version_patch_num;
|
||||
uint8_t context_id;
|
||||
uint8_t ae_id;
|
||||
uint16_t resrvd1;
|
||||
uint64_t resrvd2;
|
||||
} s1;
|
||||
struct {
|
||||
uint64_t req_rec_count;
|
||||
uint64_t resp_sent_count;
|
||||
} s2;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_init_admin_resp {
|
||||
struct icp_qat_fw_init_admin_resp_hdr init_resp_hdr;
|
||||
union {
|
||||
uint32_t resrvd2;
|
||||
struct {
|
||||
uint16_t version_minor_num;
|
||||
uint16_t version_major_num;
|
||||
} s;
|
||||
} u;
|
||||
uint64_t opaque_data;
|
||||
struct icp_qat_fw_init_admin_resp_pars init_resp_pars;
|
||||
};
|
||||
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_OK 0
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1
|
||||
#define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \
|
||||
ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags)
|
||||
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \
|
||||
ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val)
|
||||
|
||||
#define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags) \
|
||||
QAT_FIELD_GET(flags, \
|
||||
ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS, \
|
||||
ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK)
|
||||
#endif
|
||||
|
|
@ -0,0 +1,403 @@
|
|||
/*
|
||||
This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
redistributing this file, you may do so under either license.
|
||||
|
||||
GPL LICENSE SUMMARY
|
||||
Copyright(c) 2014 Intel Corporation.
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of version 2 of the GNU General Public License as
|
||||
published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
Contact Information:
|
||||
qat-linux@intel.com
|
||||
|
||||
BSD LICENSE
|
||||
Copyright(c) 2014 Intel Corporation.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _ICP_QAT_FW_LA_H_
|
||||
#define _ICP_QAT_FW_LA_H_
|
||||
#include "icp_qat_fw.h"
|
||||
|
||||
enum icp_qat_fw_la_cmd_id {
|
||||
ICP_QAT_FW_LA_CMD_CIPHER = 0,
|
||||
ICP_QAT_FW_LA_CMD_AUTH = 1,
|
||||
ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,
|
||||
ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,
|
||||
ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,
|
||||
ICP_QAT_FW_LA_CMD_TRNG_TEST = 5,
|
||||
ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,
|
||||
ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,
|
||||
ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,
|
||||
ICP_QAT_FW_LA_CMD_MGF1 = 9,
|
||||
ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,
|
||||
ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,
|
||||
ICP_QAT_FW_LA_CMD_DELIMITER = 12
|
||||
};
|
||||
|
||||
#define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
|
||||
#define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
|
||||
#define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
|
||||
#define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
|
||||
|
||||
struct icp_qat_fw_la_bulk_req {
|
||||
struct icp_qat_fw_comn_req_hdr comn_hdr;
|
||||
struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
|
||||
struct icp_qat_fw_comn_req_mid comn_mid;
|
||||
struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
|
||||
struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
|
||||
};
|
||||
|
||||
#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
|
||||
#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
|
||||
#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
|
||||
#define ICP_QAT_FW_LA_ZUC_3G_PROTO 1
|
||||
#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1
|
||||
#define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11
|
||||
#define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1
|
||||
#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1
|
||||
#define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0
|
||||
#define QAT_LA_DIGEST_IN_BUFFER_BITPOS 10
|
||||
#define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1
|
||||
#define ICP_QAT_FW_LA_SNOW_3G_PROTO 4
|
||||
#define ICP_QAT_FW_LA_GCM_PROTO 2
|
||||
#define ICP_QAT_FW_LA_CCM_PROTO 1
|
||||
#define ICP_QAT_FW_LA_NO_PROTO 0
|
||||
#define QAT_LA_PROTO_BITPOS 7
|
||||
#define QAT_LA_PROTO_MASK 0x7
|
||||
#define ICP_QAT_FW_LA_CMP_AUTH_RES 1
|
||||
#define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0
|
||||
#define QAT_LA_CMP_AUTH_RES_BITPOS 6
|
||||
#define QAT_LA_CMP_AUTH_RES_MASK 0x1
|
||||
#define ICP_QAT_FW_LA_RET_AUTH_RES 1
|
||||
#define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0
|
||||
#define QAT_LA_RET_AUTH_RES_BITPOS 5
|
||||
#define QAT_LA_RET_AUTH_RES_MASK 0x1
|
||||
#define ICP_QAT_FW_LA_UPDATE_STATE 1
|
||||
#define ICP_QAT_FW_LA_NO_UPDATE_STATE 0
|
||||
#define QAT_LA_UPDATE_STATE_BITPOS 4
|
||||
#define QAT_LA_UPDATE_STATE_MASK 0x1
|
||||
#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0
|
||||
#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1
|
||||
#define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3
|
||||
#define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1
|
||||
#define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0
|
||||
#define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1
|
||||
#define QAT_LA_CIPH_IV_FLD_BITPOS 2
|
||||
#define QAT_LA_CIPH_IV_FLD_MASK 0x1
|
||||
#define ICP_QAT_FW_LA_PARTIAL_NONE 0
|
||||
#define ICP_QAT_FW_LA_PARTIAL_START 1
|
||||
#define ICP_QAT_FW_LA_PARTIAL_MID 3
|
||||
#define ICP_QAT_FW_LA_PARTIAL_END 2
|
||||
#define QAT_LA_PARTIAL_BITPOS 0
|
||||
#define QAT_LA_PARTIAL_MASK 0x3
|
||||
#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
|
||||
cmp_auth, ret_auth, update_state, \
|
||||
ciph_iv, ciphcfg, partial) \
|
||||
(((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \
|
||||
QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \
|
||||
((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \
|
||||
QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \
|
||||
((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \
|
||||
QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \
|
||||
((proto & QAT_LA_PROTO_MASK) << \
|
||||
QAT_LA_PROTO_BITPOS) | \
|
||||
((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \
|
||||
QAT_LA_CMP_AUTH_RES_BITPOS) | \
|
||||
((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \
|
||||
QAT_LA_RET_AUTH_RES_BITPOS) | \
|
||||
((update_state & QAT_LA_UPDATE_STATE_MASK) << \
|
||||
QAT_LA_UPDATE_STATE_BITPOS) | \
|
||||
((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \
|
||||
QAT_LA_CIPH_IV_FLD_BITPOS) | \
|
||||
((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \
|
||||
QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \
|
||||
((partial & QAT_LA_PARTIAL_MASK) << \
|
||||
QAT_LA_PARTIAL_BITPOS))
|
||||
|
||||
#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \
|
||||
QAT_LA_CIPH_IV_FLD_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
|
||||
QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
|
||||
QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
|
||||
QAT_LA_GCM_IV_LEN_FLAG_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_PROTO_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \
|
||||
QAT_LA_CMP_AUTH_RES_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \
|
||||
QAT_LA_RET_AUTH_RES_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
|
||||
QAT_LA_DIGEST_IN_BUFFER_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \
|
||||
QAT_LA_UPDATE_STATE_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_PARTIAL_GET(flags) \
|
||||
QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \
|
||||
QAT_LA_PARTIAL_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \
|
||||
QAT_LA_CIPH_IV_FLD_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
|
||||
QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
|
||||
QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
|
||||
QAT_LA_GCM_IV_LEN_FLAG_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_PROTO_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
|
||||
QAT_LA_PROTO_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \
|
||||
QAT_LA_CMP_AUTH_RES_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \
|
||||
QAT_LA_RET_AUTH_RES_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
|
||||
QAT_LA_DIGEST_IN_BUFFER_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \
|
||||
QAT_LA_UPDATE_STATE_MASK)
|
||||
|
||||
#define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \
|
||||
QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
|
||||
QAT_LA_PARTIAL_MASK)
|
||||
|
||||
struct icp_qat_fw_cipher_req_hdr_cd_pars {
|
||||
union {
|
||||
struct {
|
||||
uint64_t content_desc_addr;
|
||||
uint16_t content_desc_resrvd1;
|
||||
uint8_t content_desc_params_sz;
|
||||
uint8_t content_desc_hdr_resrvd2;
|
||||
uint32_t content_desc_resrvd3;
|
||||
} s;
|
||||
struct {
|
||||
uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
|
||||
} s1;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
|
||||
union {
|
||||
struct {
|
||||
uint64_t content_desc_addr;
|
||||
uint16_t content_desc_resrvd1;
|
||||
uint8_t content_desc_params_sz;
|
||||
uint8_t content_desc_hdr_resrvd2;
|
||||
uint32_t content_desc_resrvd3;
|
||||
} s;
|
||||
struct {
|
||||
uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
|
||||
} sl;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_cipher_cd_ctrl_hdr {
|
||||
uint8_t cipher_state_sz;
|
||||
uint8_t cipher_key_sz;
|
||||
uint8_t cipher_cfg_offset;
|
||||
uint8_t next_curr_id;
|
||||
uint8_t cipher_padding_sz;
|
||||
uint8_t resrvd1;
|
||||
uint16_t resrvd2;
|
||||
uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
|
||||
};
|
||||
|
||||
struct icp_qat_fw_auth_cd_ctrl_hdr {
|
||||
uint32_t resrvd1;
|
||||
uint8_t resrvd2;
|
||||
uint8_t hash_flags;
|
||||
uint8_t hash_cfg_offset;
|
||||
uint8_t next_curr_id;
|
||||
uint8_t resrvd3;
|
||||
uint8_t outer_prefix_sz;
|
||||
uint8_t final_sz;
|
||||
uint8_t inner_res_sz;
|
||||
uint8_t resrvd4;
|
||||
uint8_t inner_state1_sz;
|
||||
uint8_t inner_state2_offset;
|
||||
uint8_t inner_state2_sz;
|
||||
uint8_t outer_config_offset;
|
||||
uint8_t outer_state1_sz;
|
||||
uint8_t outer_res_sz;
|
||||
uint8_t outer_prefix_offset;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
|
||||
uint8_t cipher_state_sz;
|
||||
uint8_t cipher_key_sz;
|
||||
uint8_t cipher_cfg_offset;
|
||||
uint8_t next_curr_id_cipher;
|
||||
uint8_t cipher_padding_sz;
|
||||
uint8_t hash_flags;
|
||||
uint8_t hash_cfg_offset;
|
||||
uint8_t next_curr_id_auth;
|
||||
uint8_t resrvd1;
|
||||
uint8_t outer_prefix_sz;
|
||||
uint8_t final_sz;
|
||||
uint8_t inner_res_sz;
|
||||
uint8_t resrvd2;
|
||||
uint8_t inner_state1_sz;
|
||||
uint8_t inner_state2_offset;
|
||||
uint8_t inner_state2_sz;
|
||||
uint8_t outer_config_offset;
|
||||
uint8_t outer_state1_sz;
|
||||
uint8_t outer_res_sz;
|
||||
uint8_t outer_prefix_offset;
|
||||
};
|
||||
|
||||
#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
|
||||
#define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
|
||||
#define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240
|
||||
#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \
|
||||
(sizeof(struct icp_qat_fw_la_cipher_req_params_t))
|
||||
#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
|
||||
|
||||
struct icp_qat_fw_la_cipher_req_params {
|
||||
uint32_t cipher_offset;
|
||||
uint32_t cipher_length;
|
||||
union {
|
||||
uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
|
||||
struct {
|
||||
uint64_t cipher_IV_ptr;
|
||||
uint64_t resrvd1;
|
||||
} s;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_la_auth_req_params {
|
||||
uint32_t auth_off;
|
||||
uint32_t auth_len;
|
||||
union {
|
||||
uint64_t auth_partial_st_prefix;
|
||||
uint64_t aad_adr;
|
||||
} u1;
|
||||
uint64_t auth_res_addr;
|
||||
union {
|
||||
uint8_t inner_prefix_sz;
|
||||
uint8_t aad_sz;
|
||||
} u2;
|
||||
uint8_t resrvd1;
|
||||
uint8_t hash_state_sz;
|
||||
uint8_t auth_res_sz;
|
||||
} __packed;
|
||||
|
||||
struct icp_qat_fw_la_auth_req_params_resrvd_flds {
|
||||
uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
|
||||
union {
|
||||
uint8_t inner_prefix_sz;
|
||||
uint8_t aad_sz;
|
||||
} u2;
|
||||
uint8_t resrvd1;
|
||||
uint16_t resrvd2;
|
||||
};
|
||||
|
||||
struct icp_qat_fw_la_resp {
|
||||
struct icp_qat_fw_comn_resp_hdr comn_resp;
|
||||
uint64_t opaque_data;
|
||||
uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
|
||||
};
|
||||
#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
|
||||
((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
|
||||
ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
|
||||
|
||||
#define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
|
||||
{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \
|
||||
((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
|
||||
& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
|
||||
((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
|
||||
& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
|
||||
|
||||
#define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \
|
||||
(((cd_ctrl_hdr_t)->next_curr_id_cipher) \
|
||||
& ICP_QAT_FW_COMN_CURR_ID_MASK)
|
||||
|
||||
#define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \
|
||||
{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \
|
||||
((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
|
||||
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
|
||||
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
|
||||
|
||||
#define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \
|
||||
((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
|
||||
>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
|
||||
|
||||
#define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
|
||||
{ (cd_ctrl_hdr_t)->next_curr_id_auth = \
|
||||
((((cd_ctrl_hdr_t)->next_curr_id_auth) \
|
||||
& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
|
||||
((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
|
||||
& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
|
||||
|
||||
#define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \
|
||||
(((cd_ctrl_hdr_t)->next_curr_id_auth) \
|
||||
& ICP_QAT_FW_COMN_CURR_ID_MASK)
|
||||
|
||||
#define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \
|
||||
{ (cd_ctrl_hdr_t)->next_curr_id_auth = \
|
||||
((((cd_ctrl_hdr_t)->next_curr_id_auth) \
|
||||
& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
|
||||
((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
redistributing this file, you may do so under either license.
|
||||
|
||||
GPL LICENSE SUMMARY
|
||||
Copyright(c) 2014 Intel Corporation.
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of version 2 of the GNU General Public License as
|
||||
published by the Free Software Foundation.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
Contact Information:
|
||||
qat-linux@intel.com
|
||||
|
||||
BSD LICENSE
|
||||
Copyright(c) 2014 Intel Corporation.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in
|
||||
the documentation and/or other materials provided with the
|
||||
distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived
|
||||
from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _ICP_QAT_HW_H_
|
||||
#define _ICP_QAT_HW_H_
|
||||
|
||||
enum icp_qat_hw_ae_id {
|
||||
ICP_QAT_HW_AE_0 = 0,
|
||||
ICP_QAT_HW_AE_1 = 1,
|
||||
ICP_QAT_HW_AE_2 = 2,
|
||||
ICP_QAT_HW_AE_3 = 3,
|
||||
ICP_QAT_HW_AE_4 = 4,
|
||||
ICP_QAT_HW_AE_5 = 5,
|
||||
ICP_QAT_HW_AE_6 = 6,
|
||||
ICP_QAT_HW_AE_7 = 7,
|
||||
ICP_QAT_HW_AE_8 = 8,
|
||||
ICP_QAT_HW_AE_9 = 9,
|
||||
ICP_QAT_HW_AE_10 = 10,
|
||||
ICP_QAT_HW_AE_11 = 11,
|
||||
ICP_QAT_HW_AE_DELIMITER = 12
|
||||
};
|
||||
|
||||
enum icp_qat_hw_qat_id {
|
||||
ICP_QAT_HW_QAT_0 = 0,
|
||||
ICP_QAT_HW_QAT_1 = 1,
|
||||
ICP_QAT_HW_QAT_2 = 2,
|
||||
ICP_QAT_HW_QAT_3 = 3,
|
||||
ICP_QAT_HW_QAT_4 = 4,
|
||||
ICP_QAT_HW_QAT_5 = 5,
|
||||
ICP_QAT_HW_QAT_DELIMITER = 6
|
||||
};
|
||||
|
||||
enum icp_qat_hw_auth_algo {
|
||||
ICP_QAT_HW_AUTH_ALGO_NULL = 0,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
|
||||
ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
|
||||
ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
|
||||
ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
|
||||
ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
|
||||
ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
|
||||
ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
|
||||
ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
|
||||
ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
|
||||
ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
|
||||
ICP_QAT_HW_AUTH_RESERVED_1 = 15,
|
||||
ICP_QAT_HW_AUTH_RESERVED_2 = 16,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
|
||||
ICP_QAT_HW_AUTH_RESERVED_3 = 18,
|
||||
ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
|
||||
ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
|
||||
};
|
||||
|
||||
enum icp_qat_hw_auth_mode {
|
||||
ICP_QAT_HW_AUTH_MODE0 = 0,
|
||||
ICP_QAT_HW_AUTH_MODE1 = 1,
|
||||
ICP_QAT_HW_AUTH_MODE2 = 2,
|
||||
ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
|
||||
};
|
||||
|
||||
struct icp_qat_hw_auth_config {
|
||||
uint32_t config;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
#define QAT_AUTH_MODE_BITPOS 4
|
||||
#define QAT_AUTH_MODE_MASK 0xF
|
||||
#define QAT_AUTH_ALGO_BITPOS 0
|
||||
#define QAT_AUTH_ALGO_MASK 0xF
|
||||
#define QAT_AUTH_CMP_BITPOS 8
|
||||
#define QAT_AUTH_CMP_MASK 0x7F
|
||||
#define QAT_AUTH_SHA3_PADDING_BITPOS 16
|
||||
#define QAT_AUTH_SHA3_PADDING_MASK 0x1
|
||||
#define QAT_AUTH_ALGO_SHA3_BITPOS 22
|
||||
#define QAT_AUTH_ALGO_SHA3_MASK 0x3
|
||||
#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
|
||||
((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
|
||||
(((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
|
||||
(((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
|
||||
QAT_AUTH_ALGO_SHA3_BITPOS) | \
|
||||
(((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
|
||||
(algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
|
||||
& QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
|
||||
(((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
|
||||
|
||||
struct icp_qat_hw_auth_counter {
|
||||
__be32 counter;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
#define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
|
||||
#define QAT_AUTH_COUNT_BITPOS 0
|
||||
#define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
|
||||
(((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
|
||||
|
||||
struct icp_qat_hw_auth_setup {
|
||||
struct icp_qat_hw_auth_config auth_config;
|
||||
struct icp_qat_hw_auth_counter auth_counter;
|
||||
};
|
||||
|
||||
#define QAT_HW_DEFAULT_ALIGNMENT 8
|
||||
#define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n-1)))
|
||||
#define ICP_QAT_HW_NULL_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_MD5_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_SHA1_STATE1_SZ 20
|
||||
#define ICP_QAT_HW_SHA224_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_SHA256_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_SHA384_STATE1_SZ 64
|
||||
#define ICP_QAT_HW_SHA512_STATE1_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
|
||||
#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
|
||||
#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
|
||||
#define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
|
||||
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
|
||||
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
|
||||
#define ICP_QAT_HW_NULL_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_MD5_STATE2_SZ 16
|
||||
#define ICP_QAT_HW_SHA1_STATE2_SZ 20
|
||||
#define ICP_QAT_HW_SHA224_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_SHA256_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA384_STATE2_SZ 64
|
||||
#define ICP_QAT_HW_SHA512_STATE2_SZ 64
|
||||
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
|
||||
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
|
||||
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
|
||||
#define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
|
||||
#define ICP_QAT_HW_F9_IK_SZ 16
|
||||
#define ICP_QAT_HW_F9_FK_SZ 16
|
||||
#define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
|
||||
ICP_QAT_HW_F9_FK_SZ)
|
||||
#define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
|
||||
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
|
||||
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
|
||||
#define ICP_QAT_HW_GALOIS_H_SZ 16
|
||||
#define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
|
||||
#define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
|
||||
|
||||
struct icp_qat_hw_auth_sha512 {
|
||||
struct icp_qat_hw_auth_setup inner_setup;
|
||||
uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
|
||||
struct icp_qat_hw_auth_setup outer_setup;
|
||||
uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
|
||||
};
|
||||
|
||||
struct icp_qat_hw_auth_algo_blk {
|
||||
struct icp_qat_hw_auth_sha512 sha;
|
||||
};
|
||||
|
||||
#define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
|
||||
#define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
|
||||
|
||||
enum icp_qat_hw_cipher_algo {
|
||||
ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
|
||||
ICP_QAT_HW_CIPHER_ALGO_DES = 1,
|
||||
ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
|
||||
ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
|
||||
ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
|
||||
ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
|
||||
ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
|
||||
ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
|
||||
ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
|
||||
ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
|
||||
ICP_QAT_HW_CIPHER_DELIMITER = 10
|
||||
};
|
||||
|
||||
enum icp_qat_hw_cipher_mode {
|
||||
ICP_QAT_HW_CIPHER_ECB_MODE = 0,
|
||||
ICP_QAT_HW_CIPHER_CBC_MODE = 1,
|
||||
ICP_QAT_HW_CIPHER_CTR_MODE = 2,
|
||||
ICP_QAT_HW_CIPHER_F8_MODE = 3,
|
||||
ICP_QAT_HW_CIPHER_XTS_MODE = 6,
|
||||
ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
|
||||
};
|
||||
|
||||
struct icp_qat_hw_cipher_config {
|
||||
uint32_t val;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
enum icp_qat_hw_cipher_dir {
|
||||
ICP_QAT_HW_CIPHER_ENCRYPT = 0,
|
||||
ICP_QAT_HW_CIPHER_DECRYPT = 1,
|
||||
};
|
||||
|
||||
enum icp_qat_hw_cipher_convert {
|
||||
ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
|
||||
ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
|
||||
};
|
||||
|
||||
#define QAT_CIPHER_MODE_BITPOS 4
|
||||
#define QAT_CIPHER_MODE_MASK 0xF
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#define QAT_CIPHER_ALGO_BITPOS 0
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#define QAT_CIPHER_ALGO_MASK 0xF
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#define QAT_CIPHER_CONVERT_BITPOS 9
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#define QAT_CIPHER_CONVERT_MASK 0x1
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#define QAT_CIPHER_DIR_BITPOS 8
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#define QAT_CIPHER_DIR_MASK 0x1
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#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
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#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
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#define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
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(((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
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((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
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((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
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((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
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||||
#define ICP_QAT_HW_DES_BLK_SZ 8
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||||
#define ICP_QAT_HW_3DES_BLK_SZ 8
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#define ICP_QAT_HW_NULL_BLK_SZ 8
|
||||
#define ICP_QAT_HW_AES_BLK_SZ 16
|
||||
#define ICP_QAT_HW_KASUMI_BLK_SZ 8
|
||||
#define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
|
||||
#define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
|
||||
#define ICP_QAT_HW_NULL_KEY_SZ 256
|
||||
#define ICP_QAT_HW_DES_KEY_SZ 8
|
||||
#define ICP_QAT_HW_3DES_KEY_SZ 24
|
||||
#define ICP_QAT_HW_AES_128_KEY_SZ 16
|
||||
#define ICP_QAT_HW_AES_192_KEY_SZ 24
|
||||
#define ICP_QAT_HW_AES_256_KEY_SZ 32
|
||||
#define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_KASUMI_KEY_SZ 16
|
||||
#define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
|
||||
QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
|
||||
#define ICP_QAT_HW_ARC4_KEY_SZ 256
|
||||
#define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
|
||||
#define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
|
||||
#define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
|
||||
#define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
|
||||
#define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
|
||||
#define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024
|
||||
|
||||
struct icp_qat_hw_cipher_aes256_f8 {
|
||||
struct icp_qat_hw_cipher_config cipher_config;
|
||||
uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
|
||||
};
|
||||
|
||||
struct icp_qat_hw_cipher_algo_blk {
|
||||
struct icp_qat_hw_cipher_aes256_f8 aes;
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue