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drm/nouveau/kms/nv50-: add fp16 scanout support 

Older hardware seems to want 0..1024 values, while new hardware takes
0..1 values. We set the gain to 1024 for the earlier display classes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
alistair/sunxi64-5.4-dsi
Ilia Mirkin 2019-05-27 22:58:37 -04:00 committed by Ben Skeggs
parent ebf8ca6b3d
commit 38a7224323
7 changed files with 66 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/gpu/drm/nouveau/dispnv50/base507c.c
View File

@ -58,12 +58,21 @@ static void
base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
{
u32 *push;
if ((push = evo_wait(&wndw->wndw, 10))) {
if ((push = evo_wait(&wndw->wndw, 13))) {
evo_mthd(push, 0x0084, 1);
evo_data(push, asyw->image.mode << 8 |
asyw->image.interval << 4);
evo_mthd(push, 0x00c0, 1);
evo_data(push, asyw->image.handle[0]);
if (asyw->image.format == 0xca) {
evo_mthd(push, 0x0110, 2);
evo_data(push, 1);
evo_data(push, 0x6400);
} else {
evo_mthd(push, 0x0110, 2);
evo_data(push, 0);
evo_data(push, 0);
}
evo_mthd(push, 0x0800, 5);
evo_data(push, asyw->image.offset[0] >> 8);
evo_data(push, 0x00000000);
@ -181,9 +190,6 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
const struct drm_framebuffer *fb = asyw->state.fb;
int ret;
if (!fb->format->depth)
return -EINVAL;
ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
DRM_PLANE_HELPER_NO_SCALING,
DRM_PLANE_HELPER_NO_SCALING,
@ -202,6 +208,14 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
asyh->base.y = asyw->state.src.y1 >> 16;
asyh->base.w = asyw->state.fb->width;
asyh->base.h = asyw->state.fb->height;
/* Some newer formats, esp FP16 ones, don't have a
* "depth". There's nothing that really makes sense there
* either, so just set it to the implicit bit count.
*/
if (!asyh->base.depth)
asyh->base.depth = asyh->base.cpp * 8;
return 0;
}
@ -217,6 +231,8 @@ base507c_format[] = {
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ABGR16161616F,
0
};

11
drivers/gpu/drm/nouveau/dispnv50/base827c.c
View File

@ -25,12 +25,21 @@ static void
base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
{
u32 *push;
if ((push = evo_wait(&wndw->wndw, 10))) {
if ((push = evo_wait(&wndw->wndw, 13))) {
evo_mthd(push, 0x0084, 1);
evo_data(push, asyw->image.mode << 8 |
asyw->image.interval << 4);
evo_mthd(push, 0x00c0, 1);
evo_data(push, asyw->image.handle[0]);
if (asyw->image.format == 0xca) {
evo_mthd(push, 0x0110, 2);
evo_data(push, 1);
evo_data(push, 0x6400);
} else {
evo_mthd(push, 0x0110, 2);
evo_data(push, 0);
evo_data(push, 0);
}
evo_mthd(push, 0x0800, 5);
evo_data(push, asyw->image.offset[0] >> 8);
evo_data(push, 0x00000000);

2
drivers/gpu/drm/nouveau/dispnv50/base917c.c
View File

@ -36,6 +36,8 @@ base917c_format[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ABGR16161616F,
0
};

17
drivers/gpu/drm/nouveau/dispnv50/ovly907e.c
View File

@ -61,10 +61,25 @@ ovly907e = {
.update = ovly507e_update,
};
static const u32
ovly907e_format[] = {
DRM_FORMAT_YUYV,
DRM_FORMAT_UYVY,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ABGR16161616F,
0
};
int
ovly907e_new(struct nouveau_drm *drm, int head, s32 oclass,
struct nv50_wndw **pwndw)
{
return ovly507e_new_(&ovly907e, ovly827e_format, drm, head, oclass,
return ovly507e_new_(&ovly907e, ovly907e_format, drm, head, oclass,
0x00000004 << (head * 4), pwndw);
}

2
drivers/gpu/drm/nouveau/dispnv50/ovly917e.c
View File

@ -33,6 +33,8 @@ ovly917e_format[] = {
DRM_FORMAT_ABGR2101010,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ABGR16161616F,
0
};

26
drivers/gpu/drm/nouveau/dispnv50/wndw.c
View File

@ -204,18 +204,20 @@ static int
nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
{
switch (asyw->state.fb->format->format) {
case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
case DRM_FORMAT_XRGB8888 :
case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
case DRM_FORMAT_XRGB1555 :
case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
case DRM_FORMAT_XBGR8888 :
case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_ARGB2101010: asyw->image.format = 0xdf; break;
case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
case DRM_FORMAT_XRGB8888 :
case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
case DRM_FORMAT_XRGB1555 :
case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
case DRM_FORMAT_XBGR2101010 :
case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break;
case DRM_FORMAT_XBGR8888 :
case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
case DRM_FORMAT_XRGB2101010 :
case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break;
case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break;
default:
return -EINVAL;
}

2
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
View File

@ -216,6 +216,8 @@ wndwc37e_format[] = {
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_ABGR16161616F,
0
};