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cxgb4: handle serial flash interrupt 

If SF bit is not cleared in PL_INT_CAUSE, subsequent non-data
interrupts are not raised.  Enable SF bit in Global Interrupt
Mask and handle it as non-fatal and hence eventually clear it.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Ganesh Goudar 2017-06-14 00:45:43 +05:30 committed by David S. Miller
parent 4798a714d6
commit 38b6ec5008
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
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@ -4462,7 +4462,7 @@ static void pl_intr_handler(struct adapter *adap)
#define PF_INTR_MASK (PFSW_F)
#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
CPL_SWITCH_F | SGE_F | ULP_TX_F)
CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
/**
* t4_slow_intr_handler - control path interrupt handler