ARM: dts: Add support for OX820 and Pogoplug V3
Add device tree for the Oxford Seminconductor OX820 SoC and the Cloud Engines PogoPlug v3 board. Add the SoC and board compatible strings to oxnas bindings. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>hifive-unleashed-5.1
Neil Armstrong
parent
1001354ca3
commit
38d4a53733
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@ -5,5 +5,10 @@ Boards with the OX810SE SoC shall have the following properties:
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Required root node property:
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compatible: "oxsemi,ox810se"
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Boards with the OX820 SoC shall have the following properties:
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Required root node property:
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compatible: "oxsemi,ox820"
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Board compatible values:
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- "wd,mbwe" (OX810SE)
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- "cloudengines,pogoplugv3" (OX820)
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@ -604,7 +604,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
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dtb-$(CONFIG_ARCH_PRIMA2) += \
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prima2-evb.dtb
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dtb-$(CONFIG_ARCH_OXNAS) += \
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wd-mbwe.dtb
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wd-mbwe.dtb \
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cloudengines-pogoplug-series-3.dtb
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dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8060-dragonboard.dtb \
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qcom-apq8064-arrow-sd-600eval.dtb \
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@ -0,0 +1,94 @@
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/*
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* cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
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*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*
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* Licensed under GPLv2 or later
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*/
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/dts-v1/;
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#include "ox820.dtsi"
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/ {
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model = "Cloud Engines PogoPlug Series 3";
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compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
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chosen {
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bootargs = "earlyprintk";
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stdout-path = "serial0:115200n8";
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};
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memory {
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/* 128Mbytes DDR */
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reg = <0x60000000 0x8000000>;
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};
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aliases {
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serial0 = &uart0;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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};
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leds {
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compatible = "gpio-leds";
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blue {
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label = "pogoplug:blue";
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gpios = <&gpio0 2 0>;
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default-state = "keep";
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};
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orange {
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label = "pogoplug:orange";
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gpios = <&gpio1 16 1>;
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default-state = "keep";
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};
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green {
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label = "pogoplug:green";
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gpios = <&gpio1 17 1>;
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default-state = "keep";
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};
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};
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};
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&uart0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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};
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&nandc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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nand@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "hamming";
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partition@0 {
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label = "boot";
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reg = <0x00000000 0x00e00000>;
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read-only;
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};
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partition@e00000 {
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label = "ubi";
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reg = <0x00e00000 0x07200000>;
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};
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};
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};
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ða {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_etha_mdio>;
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};
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@ -0,0 +1,296 @@
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/*
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* ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
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*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*
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* Licensed under GPLv2 or later
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "oxsemi,ox820";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "oxsemi,ox820-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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clocks = <&armclk>;
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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clocks = <&armclk>;
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reg = <1>;
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};
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};
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memory {
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/* Max 512MB @ 0x60000000 */
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reg = <0x60000000 0x20000000>;
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};
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clocks {
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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gmacclk: gmacclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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sysclk: sysclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&osc>;
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};
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plla: plla {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <850000000>;
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};
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armclk: armclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&plla>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&gic>;
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nandc: nand-controller@41000000 {
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compatible = "oxsemi,ox820-nand";
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reg = <0x41000000 0x100000>;
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clocks = <&stdclk 11>;
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resets = <&reset 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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etha: ethernet@40400000 {
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compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
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reg = <0x40400000 0x2000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq";
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mac-address = [000000000000]; /* Filled in by U-Boot */
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phy-mode = "rgmii";
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clocks = <&stdclk 9>, <&gmacclk>;
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clock-names = "gmac", "stmmaceth";
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resets = <&reset 6>;
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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status = "disabled";
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};
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apb-bridge@44000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x44000000 0x1000000>;
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pinctrl: pinctrl {
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compatible = "oxsemi,ox820-pinctrl";
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/* Regmap for sys registers */
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oxsemi,sys-ctrl = <&sys>;
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pinctrl_uart0: uart0 {
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uart0 {
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pins = "gpio30", "gpio31";
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function = "fct5";
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};
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};
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pinctrl_uart0_modem: uart0_modem {
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uart0_modem_a {
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pins = "gpio24", "gpio24", "gpio26", "gpio27";
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function = "fct4";
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};
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uart0_modem_b {
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pins = "gpio28", "gpio29";
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function = "fct5";
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};
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};
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pinctrl_uart1: uart1 {
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uart1 {
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pins = "gpio7", "gpio8";
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function = "fct4";
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};
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};
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pinctrl_uart1_modem: uart1_modem {
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uart1_modem {
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pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
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function = "fct4";
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};
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};
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pinctrl_etha_mdio: etha_mdio {
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etha_mdio {
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pins = "gpio3", "gpio4";
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function = "fct1";
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};
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};
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pinctrl_nand: nand {
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nand {
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pins = "gpio12", "gpio13", "gpio14", "gpio15",
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"gpio16", "gpio17", "gpio18", "gpio19",
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"gpio20", "gpio21", "gpio22", "gpio23",
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"gpio24";
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function = "fct1";
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};
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};
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};
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gpio0: gpio@000000 {
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compatible = "oxsemi,ox820-gpio";
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reg = <0x000000 0x100000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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ngpios = <32>;
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oxsemi,gpio-bank = <0>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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gpio1: gpio@100000 {
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compatible = "oxsemi,ox820-gpio";
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reg = <0x100000 0x100000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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ngpios = <18>;
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oxsemi,gpio-bank = <1>;
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gpio-ranges = <&pinctrl 0 32 18>;
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};
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uart0: serial@200000 {
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compatible = "ns16550a";
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reg = <0x200000 0x100000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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clocks = <&sysclk>;
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resets = <&reset 17>;
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};
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uart1: serial@300000 {
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compatible = "ns16550a";
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reg = <0x200000 0x100000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <0>;
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fifo-size = <16>;
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reg-io-width = <1>;
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current-speed = <115200>;
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no-loopback-test;
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status = "disabled";
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clocks = <&sysclk>;
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resets = <&reset 18>;
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};
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rps@400000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x400000 0x100000>;
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intc: interrupt-controller@0 {
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compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
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interrupt-controller;
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reg = <0 0x200>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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valid-mask = <0xFFFFFFFF>;
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clear-mask = <0>;
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};
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timer0: timer@200 {
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compatible = "oxsemi,ox820-rps-timer";
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reg = <0x200 0x40>;
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clocks = <&sysclk>;
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interrupt-parent = <&intc>;
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interrupts = <4>;
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};
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};
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sys: sys-ctrl@e00000 {
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compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
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reg = <0xe00000 0x200000>;
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reset: reset-controller {
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compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
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#reset-cells = <1>;
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};
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stdclk: stdclk {
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compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
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#clock-cells = <1>;
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};
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};
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};
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apb-bridge@47000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0x47000000 0x1000000>;
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scu: scu@0 {
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compatible = "arm,arm11mp-scu";
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reg = <0x0 0x100>;
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};
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local-timer@600 {
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compatible = "arm,arm11mp-twd-timer";
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reg = <0x600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&armclk>;
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};
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gic: gic@1000 {
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compatible = "arm,arm11mp-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1000 0x1000>,
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<0x100 0x500>;
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};
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};
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};
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};
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