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[ARM] pxa: move common GPIO handling code into plat-pxa 

1. add common GPIO handling code into [arch/arm/plat-pxa]

2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors
   should implement its own <mach/gpio.h>, provide the following required
   definitions and '#include <plat/gpio.h>' in the end:

   - GPIO_REGS_VIRT for mapped virtual address of the GPIO registers'
     physical I/O memory

   - macros of GPLR(), GPSR(), GPDR() for constant optimization for
     functions gpio_{set,get}_value() (so that bit-bang code can still
     have tolerable performance)

   - NR_BUILTIN_GPIO for the number of onchip GPIO

   - definitions of __gpio_is_inverted() and __gpio_is_occupied(), they
     can be either macros or inlined functions

Signed-off-by: Eric Miao <eric.miao@marvell.com>
hifive-unleashed-5.1
Eric Miao 2009-01-20 12:09:06 +08:00
parent bd5ce43323
commit 38f539a608
5 changed files with 66 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-pxa/Makefile
View File

@ -4,7 +4,7 @@
# Common support (must be linked before board specific support)
obj-y += clock.o devices.o generic.o irq.o \
time.o gpio.o reset.o
time.o reset.o
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
ifeq ($(CONFIG_CPU_FREQ),y)

32
arch/arm/mach-pxa/include/mach/gpio.h
View File

@ -99,40 +99,12 @@
#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
* Those cases currently cause holes in the GPIO number space, the
* actual number of the last GPIO is recorded by 'pxa_last_gpio'.
*/
extern int pxa_last_gpio;
#define NR_BUILTIN_GPIO 128
static inline int gpio_get_value(unsigned gpio)
{
if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
return GPLR(gpio) & GPIO_bit(gpio);
else
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
if (value)
GPSR(gpio) = GPIO_bit(gpio);
else
GPCR(gpio) = GPIO_bit(gpio);
} else {
__gpio_set_value(gpio, value);
}
}
#define gpio_cansleep __gpio_cansleep
#define gpio_to_bank(gpio) ((gpio) >> 5)
#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
#ifdef CONFIG_CPU_PXA26x
/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
* as well as their Alternate Function value being '1' for GPIO in GAFRx.
@ -165,7 +137,5 @@ static inline int __gpio_is_occupied(unsigned gpio)
return GPDR(gpio) & GPIO_bit(gpio);
}
typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
#include <plat/gpio.h>
#endif

1
arch/arm/plat-pxa/Makefile
View File

@ -4,3 +4,4 @@
obj-y := dma.o
obj-$(CONFIG_GENERIC_GPIO) += gpio.o

30
arch/arm/mach-pxa/gpio.c → arch/arm/plat-pxa/gpio.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-pxa/gpio.c
* linux/arch/arm/plat-pxa/gpio.c
*
* Generic PXA GPIO handling
*
@ -22,34 +22,6 @@
int pxa_last_gpio;
/*
* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
* one set of registers. The register offsets are organized below:
*
* GPLR GPDR GPSR GPCR GRER GFER GEDR
* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
*
* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
*
* NOTE:
* BANK 3 is only available on PXA27x and later processors.
* BANK 4 and 5 are only available on PXA935
*/
#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
#define GPLR_OFFSET 0x00
#define GPDR_OFFSET 0x0C
#define GPSR_OFFSET 0x18
#define GPCR_OFFSET 0x24
#define GRER_OFFSET 0x30
#define GFER_OFFSET 0x3C
#define GEDR_OFFSET 0x48
struct pxa_gpio_chip {
struct gpio_chip chip;
void __iomem *regbase;

62
arch/arm/plat-pxa/include/plat/gpio.h 100644
View File

@ -0,0 +1,62 @@
#ifndef __PLAT_GPIO_H
#define __PLAT_GPIO_H
/*
* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
* one set of registers. The register offsets are organized below:
*
* GPLR GPDR GPSR GPCR GRER GFER GEDR
* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
*
* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
*
* NOTE:
* BANK 3 is only available on PXA27x and later processors.
* BANK 4 and 5 are only available on PXA935
*/
#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n))
#define GPLR_OFFSET 0x00
#define GPDR_OFFSET 0x0C
#define GPSR_OFFSET 0x18
#define GPCR_OFFSET 0x24
#define GRER_OFFSET 0x30
#define GFER_OFFSET 0x3C
#define GEDR_OFFSET 0x48
static inline int gpio_get_value(unsigned gpio)
{
if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
return GPLR(gpio) & GPIO_bit(gpio);
else
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
if (value)
GPSR(gpio) = GPIO_bit(gpio);
else
GPCR(gpio) = GPIO_bit(gpio);
} else
__gpio_set_value(gpio, value);
}
#define gpio_cansleep __gpio_cansleep
/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
* Those cases currently cause holes in the GPIO number space, the
* actual number of the last GPIO is recorded by 'pxa_last_gpio'.
*/
extern int pxa_last_gpio;
typedef int (*set_wake_t)(unsigned int irq, unsigned int on);
extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
#endif /* __PLAT_GPIO_H */