net: dsa: mt7530: Add support for port 5
Adding support for port 5. Port 5 can muxed/interface to: - internal 5th GMAC of the switch; can be used as 2nd CPU port or as extra port with an external phy for a 6th ethernet port. - internal PHY of port 0 or 4; Used in most applications so that port 0 or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC. Signed-off-by: René van Dorst <opensource@vdorst.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>alistair/sunxi64-5.4-dsi
René van Dorst
David S. Miller
parent
4f358cbd05
commit
38f790a805
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@ -633,6 +633,77 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
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return ARRAY_SIZE(mt7530_mib);
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}
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static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
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{
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struct mt7530_priv *priv = ds->priv;
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u8 tx_delay = 0;
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int val;
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mutex_lock(&priv->reg_mutex);
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val = mt7530_read(priv, MT7530_MHWTRAP);
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val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
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val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
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switch (priv->p5_intf_sel) {
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case P5_INTF_SEL_PHY_P0:
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/* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
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val |= MHWTRAP_PHY0_SEL;
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/* fall through */
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case P5_INTF_SEL_PHY_P4:
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/* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
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val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
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/* Setup the MAC by default for the cpu port */
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mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
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break;
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case P5_INTF_SEL_GMAC5:
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/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
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val &= ~MHWTRAP_P5_DIS;
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break;
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case P5_DISABLED:
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interface = PHY_INTERFACE_MODE_NA;
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break;
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default:
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dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
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priv->p5_intf_sel);
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goto unlock_exit;
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}
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/* Setup RGMII settings */
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if (phy_interface_mode_is_rgmii(interface)) {
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val |= MHWTRAP_P5_RGMII_MODE;
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/* P5 RGMII RX Clock Control: delay setting for 1000M */
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mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
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/* Don't set delay in DSA mode */
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if (!dsa_is_dsa_port(priv->ds, 5) &&
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(interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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interface == PHY_INTERFACE_MODE_RGMII_ID))
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tx_delay = 4; /* n * 0.5 ns */
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/* P5 RGMII TX Clock Control: delay x */
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mt7530_write(priv, MT7530_P5RGMIITXCR,
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CSR_RGMII_TXC_CFG(0x10 + tx_delay));
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/* reduce P5 RGMII Tx driving, 8mA */
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mt7530_write(priv, MT7530_IO_DRV_CR,
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P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
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}
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mt7530_write(priv, MT7530_MHWTRAP, val);
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dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
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val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
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priv->p5_interface = interface;
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unlock_exit:
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mutex_unlock(&priv->reg_mutex);
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}
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static int
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mt7530_cpu_port_enable(struct mt7530_priv *priv,
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int port)
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@ -1169,7 +1240,10 @@ static int
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mt7530_setup(struct dsa_switch *ds)
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{
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struct mt7530_priv *priv = ds->priv;
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struct device_node *phy_node;
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struct device_node *mac_np;
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struct mt7530_dummy_poll p;
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phy_interface_t interface;
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struct device_node *dn;
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u32 id, val;
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int ret, i;
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@ -1260,6 +1334,40 @@ mt7530_setup(struct dsa_switch *ds)
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mt7530_port_disable(ds, i);
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}
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/* Setup port 5 */
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priv->p5_intf_sel = P5_DISABLED;
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interface = PHY_INTERFACE_MODE_NA;
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if (!dsa_is_unused_port(ds, 5)) {
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priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
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interface = of_get_phy_mode(ds->ports[5].dn);
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} else {
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/* Scan the ethernet nodes. look for GMAC1, lookup used phy */
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for_each_child_of_node(dn, mac_np) {
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if (!of_device_is_compatible(mac_np,
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"mediatek,eth-mac"))
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continue;
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ret = of_property_read_u32(mac_np, "reg", &id);
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if (ret < 0 || id != 1)
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continue;
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phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
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if (phy_node->parent == priv->dev->of_node->parent) {
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interface = of_get_phy_mode(mac_np);
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id = of_mdio_parse_addr(ds->dev, phy_node);
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if (id == 0)
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priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
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if (id == 4)
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priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
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}
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of_node_put(phy_node);
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break;
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}
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}
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mt7530_setup_port5(ds, interface);
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/* Flush the FDB table */
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ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
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if (ret < 0)
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@ -1284,7 +1392,16 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
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if (state->interface != PHY_INTERFACE_MODE_GMII)
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return;
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break;
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/* case 5: Port 5 is not supported! */
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case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
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if (priv->p5_interface == state->interface)
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break;
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if (!phy_interface_mode_is_rgmii(state->interface) &&
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state->interface != PHY_INTERFACE_MODE_MII &&
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state->interface != PHY_INTERFACE_MODE_GMII)
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return;
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mt7530_setup_port5(ds, state->interface);
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break;
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case 6: /* 1st cpu port */
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if (priv->p6_interface == state->interface)
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break;
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@ -1324,6 +1441,10 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
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mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
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PMCR_BACKPR_EN | PMCR_FORCE_MODE | PMCR_FORCE_LNK;
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/* Are we connected to external phy */
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if (port == 5 && dsa_is_user_port(ds, 5))
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mcr_new |= PMCR_EXT_PHY;
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switch (state->speed) {
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case SPEED_1000:
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mcr_new |= PMCR_FORCE_SPEED_1000;
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@ -1379,7 +1500,13 @@ static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
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state->interface != PHY_INTERFACE_MODE_GMII)
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goto unsupported;
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break;
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/* case 5: Port 5 not supported! */
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case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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!phy_interface_mode_is_rgmii(state->interface) &&
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state->interface != PHY_INTERFACE_MODE_MII &&
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state->interface != PHY_INTERFACE_MODE_GMII)
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goto unsupported;
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break;
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case 6: /* 1st cpu port */
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_RGMII &&
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@ -1396,15 +1523,21 @@ unsupported:
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phylink_set_port_modes(mask);
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phylink_set(mask, Autoneg);
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if (state->interface != PHY_INTERFACE_MODE_TRGMII) {
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if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
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phylink_set(mask, 1000baseT_Full);
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} else {
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phylink_set(mask, 10baseT_Half);
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phylink_set(mask, 10baseT_Full);
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phylink_set(mask, 100baseT_Half);
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phylink_set(mask, 100baseT_Full);
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phylink_set(mask, 1000baseT_Half);
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}
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phylink_set(mask, 1000baseT_Full);
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if (state->interface != PHY_INTERFACE_MODE_MII) {
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phylink_set(mask, 1000baseT_Half);
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phylink_set(mask, 1000baseT_Full);
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if (port == 5)
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phylink_set(mask, 1000baseX_Full);
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}
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}
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phylink_set(mask, Pause);
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phylink_set(mask, Asym_Pause);
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@ -186,6 +186,7 @@ enum mt7530_vlan_port_attr {
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/* Register for port MAC control register */
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#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
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#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
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#define PMCR_EXT_PHY BIT(17)
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#define PMCR_MAC_MODE BIT(16)
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#define PMCR_FORCE_MODE BIT(15)
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#define PMCR_TX_EN BIT(14)
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@ -245,6 +246,7 @@ enum mt7530_vlan_port_attr {
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/* Register for hw trap modification */
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#define MT7530_MHWTRAP 0x7804
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#define MHWTRAP_PHY0_SEL BIT(20)
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#define MHWTRAP_MANUAL BIT(16)
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#define MHWTRAP_P5_MAC_SEL BIT(13)
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#define MHWTRAP_P6_DIS BIT(8)
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@ -402,6 +404,30 @@ struct mt7530_port {
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u16 pvid;
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};
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/* Port 5 interface select definitions */
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enum p5_interface_select {
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P5_DISABLED = 0,
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P5_INTF_SEL_PHY_P0,
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P5_INTF_SEL_PHY_P4,
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P5_INTF_SEL_GMAC5,
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};
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static const char *p5_intf_modes(unsigned int p5_interface)
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{
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switch (p5_interface) {
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case P5_DISABLED:
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return "DISABLED";
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case P5_INTF_SEL_PHY_P0:
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return "PHY P0";
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case P5_INTF_SEL_PHY_P4:
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return "PHY P4";
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case P5_INTF_SEL_GMAC5:
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return "GMAC5";
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default:
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return "unknown";
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}
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}
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/* struct mt7530_priv - This is the main data structure for holding the state
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* of the driver
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* @dev: The device pointer
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@ -418,6 +444,7 @@ struct mt7530_port {
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* @reg_mutex: The lock for protecting among process accessing
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* registers
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* @p6_interface Holding the current port 6 interface
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* @p5_intf_sel: Holding the current port 5 interface select
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*/
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struct mt7530_priv {
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struct device *dev;
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@ -431,6 +458,8 @@ struct mt7530_priv {
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unsigned int id;
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bool mcm;
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phy_interface_t p6_interface;
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phy_interface_t p5_interface;
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unsigned int p5_intf_sel;
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struct mt7530_port ports[MT7530_NUM_PORTS];
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/* protect among processes for registers access*/
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