arm64: atomics: fix grossly inconsistent asm constraints for exclusives
Our uses of inline asm constraints for atomic operations are fairly
wild and varied. We basically need to guarantee the following:
1. Any instructions with barrier implications
(load-acquire/store-release) have a "memory" clobber
2. When performing exclusive accesses, the addresing mode is generated
using the "Q" constraint
3. Atomic blocks which use the condition flags, have a "cc" clobber
This patch addresses these concerns which, as well as fixing the
semantics of the code, stops GCC complaining about impossible asm
constraints.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
hifive-unleashed-5.1
Will Deacon
Catalin Marinas
parent
c0e01d5d8f
commit
3a0310eb36
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@ -49,12 +49,12 @@ static inline void atomic_add(int i, atomic_t *v)
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int result;
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asm volatile("// atomic_add\n"
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"1: ldxr %w0, [%3]\n"
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" add %w0, %w0, %w4\n"
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" stxr %w1, %w0, [%3]\n"
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"1: ldxr %w0, %2\n"
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" add %w0, %w0, %w3\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc");
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}
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@ -64,13 +64,13 @@ static inline int atomic_add_return(int i, atomic_t *v)
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int result;
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asm volatile("// atomic_add_return\n"
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"1: ldaxr %w0, [%3]\n"
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" add %w0, %w0, %w4\n"
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" stlxr %w1, %w0, [%3]\n"
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"1: ldaxr %w0, %2\n"
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" add %w0, %w0, %w3\n"
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" stlxr %w1, %w0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc", "memory");
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return result;
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}
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@ -81,12 +81,12 @@ static inline void atomic_sub(int i, atomic_t *v)
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int result;
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asm volatile("// atomic_sub\n"
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"1: ldxr %w0, [%3]\n"
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" sub %w0, %w0, %w4\n"
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" stxr %w1, %w0, [%3]\n"
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"1: ldxr %w0, %2\n"
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" sub %w0, %w0, %w3\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc");
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}
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@ -96,13 +96,13 @@ static inline int atomic_sub_return(int i, atomic_t *v)
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int result;
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asm volatile("// atomic_sub_return\n"
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"1: ldaxr %w0, [%3]\n"
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" sub %w0, %w0, %w4\n"
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" stlxr %w1, %w0, [%3]\n"
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"1: ldaxr %w0, %2\n"
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" sub %w0, %w0, %w3\n"
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" stlxr %w1, %w0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc", "memory");
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return result;
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}
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@ -113,15 +113,15 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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int oldval;
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asm volatile("// atomic_cmpxchg\n"
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"1: ldaxr %w1, [%3]\n"
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" cmp %w1, %w4\n"
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"1: ldaxr %w1, %2\n"
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" cmp %w1, %w3\n"
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" b.ne 2f\n"
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" stlxr %w0, %w5, [%3]\n"
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" stlxr %w0, %w4, %2\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (tmp), "=&r" (oldval), "+o" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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: "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
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: "Ir" (old), "r" (new)
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: "cc", "memory");
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return oldval;
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}
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@ -131,12 +131,12 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
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unsigned long tmp, tmp2;
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asm volatile("// atomic_clear_mask\n"
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"1: ldxr %0, [%3]\n"
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" bic %0, %0, %4\n"
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" stxr %w1, %0, [%3]\n"
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"1: ldxr %0, %2\n"
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" bic %0, %0, %3\n"
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" stxr %w1, %0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (tmp), "=&r" (tmp2), "+o" (*addr)
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: "r" (addr), "Ir" (mask)
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (*addr)
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: "Ir" (mask)
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: "cc");
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}
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@ -182,12 +182,12 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
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unsigned long tmp;
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asm volatile("// atomic64_add\n"
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"1: ldxr %0, [%3]\n"
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" add %0, %0, %4\n"
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" stxr %w1, %0, [%3]\n"
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"1: ldxr %0, %2\n"
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" add %0, %0, %3\n"
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" stxr %w1, %0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc");
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}
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@ -197,13 +197,13 @@ static inline long atomic64_add_return(long i, atomic64_t *v)
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unsigned long tmp;
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asm volatile("// atomic64_add_return\n"
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"1: ldaxr %0, [%3]\n"
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" add %0, %0, %4\n"
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" stlxr %w1, %0, [%3]\n"
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"1: ldaxr %0, %2\n"
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" add %0, %0, %3\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc", "memory");
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return result;
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}
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@ -214,12 +214,12 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
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unsigned long tmp;
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asm volatile("// atomic64_sub\n"
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"1: ldxr %0, [%3]\n"
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" sub %0, %0, %4\n"
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" stxr %w1, %0, [%3]\n"
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"1: ldxr %0, %2\n"
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" sub %0, %0, %3\n"
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" stxr %w1, %0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc");
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}
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@ -229,13 +229,13 @@ static inline long atomic64_sub_return(long i, atomic64_t *v)
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unsigned long tmp;
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asm volatile("// atomic64_sub_return\n"
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"1: ldaxr %0, [%3]\n"
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" sub %0, %0, %4\n"
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" stlxr %w1, %0, [%3]\n"
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"1: ldaxr %0, %2\n"
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" sub %0, %0, %3\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter), "Ir" (i)
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: "cc");
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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: "Ir" (i)
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: "cc", "memory");
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return result;
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}
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@ -246,15 +246,15 @@ static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
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unsigned long res;
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asm volatile("// atomic64_cmpxchg\n"
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"1: ldaxr %1, [%3]\n"
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" cmp %1, %4\n"
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"1: ldaxr %1, %2\n"
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" cmp %1, %3\n"
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" b.ne 2f\n"
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" stlxr %w0, %5, [%3]\n"
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" stlxr %w0, %4, %2\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (res), "=&r" (oldval), "+o" (ptr->counter)
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: "r" (&ptr->counter), "Ir" (old), "r" (new)
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: "cc");
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: "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
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: "Ir" (old), "r" (new)
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: "cc", "memory");
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return oldval;
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}
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@ -267,15 +267,15 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
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unsigned long tmp;
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asm volatile("// atomic64_dec_if_positive\n"
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"1: ldaxr %0, [%3]\n"
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"1: ldaxr %0, %2\n"
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" subs %0, %0, #1\n"
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" b.mi 2f\n"
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" stlxr %w1, %0, [%3]\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
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: "r" (&v->counter)
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: "cc");
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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:
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: "cc", "memory");
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return result;
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}
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@ -29,39 +29,39 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
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switch (size) {
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case 1:
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asm volatile("// __xchg1\n"
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"1: ldaxrb %w0, [%3]\n"
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" stlxrb %w1, %w2, [%3]\n"
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"1: ldaxrb %w0, %2\n"
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" stlxrb %w1, %w3, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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: "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr)
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: "r" (x)
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: "cc", "memory");
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break;
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case 2:
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asm volatile("// __xchg2\n"
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"1: ldaxrh %w0, [%3]\n"
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" stlxrh %w1, %w2, [%3]\n"
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"1: ldaxrh %w0, %2\n"
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" stlxrh %w1, %w3, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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: "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr)
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: "r" (x)
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: "cc", "memory");
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break;
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case 4:
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asm volatile("// __xchg4\n"
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"1: ldaxr %w0, [%3]\n"
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" stlxr %w1, %w2, [%3]\n"
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"1: ldaxr %w0, %2\n"
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" stlxr %w1, %w3, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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: "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr)
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: "r" (x)
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: "cc", "memory");
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break;
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case 8:
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asm volatile("// __xchg8\n"
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"1: ldaxr %0, [%3]\n"
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" stlxr %w1, %2, [%3]\n"
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"1: ldaxr %0, %2\n"
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" stlxr %w1, %3, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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: "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr)
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: "r" (x)
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: "cc", "memory");
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break;
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default:
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BUILD_BUG();
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@ -82,14 +82,14 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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case 1:
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do {
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asm volatile("// __cmpxchg1\n"
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" ldxrb %w1, [%2]\n"
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" ldxrb %w1, %2\n"
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" mov %w0, #0\n"
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" cmp %w1, %w3\n"
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" b.ne 1f\n"
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" stxrb %w0, %w4, [%2]\n"
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" stxrb %w0, %w4, %2\n"
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"1:\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "=&r" (res), "=&r" (oldval), "+Q" (*(u8 *)ptr)
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: "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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break;
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@ -97,29 +97,29 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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case 2:
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do {
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asm volatile("// __cmpxchg2\n"
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" ldxrh %w1, [%2]\n"
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" ldxrh %w1, %2\n"
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" mov %w0, #0\n"
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" cmp %w1, %w3\n"
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" b.ne 1f\n"
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" stxrh %w0, %w4, [%2]\n"
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" stxrh %w0, %w4, %2\n"
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"1:\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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: "=&r" (res), "=&r" (oldval), "+Q" (*(u16 *)ptr)
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: "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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break;
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case 4:
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do {
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asm volatile("// __cmpxchg4\n"
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" ldxr %w1, [%2]\n"
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" ldxr %w1, %2\n"
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" mov %w0, #0\n"
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" cmp %w1, %w3\n"
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" b.ne 1f\n"
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" stxr %w0, %w4, [%2]\n"
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" stxr %w0, %w4, %2\n"
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"1:\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "=&r" (res), "=&r" (oldval), "+Q" (*(u32 *)ptr)
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: "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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break;
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@ -127,14 +127,14 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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case 8:
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do {
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asm volatile("// __cmpxchg8\n"
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" ldxr %1, [%2]\n"
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" ldxr %1, %2\n"
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" mov %w0, #0\n"
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" cmp %1, %3\n"
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" b.ne 1f\n"
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" stxr %w0, %4, [%2]\n"
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" stxr %w0, %4, %2\n"
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"1:\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "=&r" (res), "=&r" (oldval), "+Q" (*(u64 *)ptr)
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: "Ir" (old), "r" (new)
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: "cc");
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} while (res);
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break;
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@ -39,7 +39,7 @@
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" .popsection\n" \
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
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: "r" (oparg), "Ir" (-EFAULT) \
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: "cc")
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: "cc", "memory")
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static inline int
|
||||
futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
||||
|
|
|
|||
|
|
@ -45,13 +45,13 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
|
|||
asm volatile(
|
||||
" sevl\n"
|
||||
"1: wfe\n"
|
||||
"2: ldaxr %w0, [%1]\n"
|
||||
"2: ldaxr %w0, %1\n"
|
||||
" cbnz %w0, 1b\n"
|
||||
" stxr %w0, %w2, [%1]\n"
|
||||
" stxr %w0, %w2, %1\n"
|
||||
" cbnz %w0, 2b\n"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&lock->lock), "r" (1)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "+Q" (lock->lock)
|
||||
: "r" (1)
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
static inline int arch_spin_trylock(arch_spinlock_t *lock)
|
||||
|
|
@ -59,13 +59,13 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
|
|||
unsigned int tmp;
|
||||
|
||||
asm volatile(
|
||||
" ldaxr %w0, [%1]\n"
|
||||
" ldaxr %w0, %1\n"
|
||||
" cbnz %w0, 1f\n"
|
||||
" stxr %w0, %w2, [%1]\n"
|
||||
" stxr %w0, %w2, %1\n"
|
||||
"1:\n"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&lock->lock), "r" (1)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "+Q" (lock->lock)
|
||||
: "r" (1)
|
||||
: "cc", "memory");
|
||||
|
||||
return !tmp;
|
||||
}
|
||||
|
|
@ -73,8 +73,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
|
|||
static inline void arch_spin_unlock(arch_spinlock_t *lock)
|
||||
{
|
||||
asm volatile(
|
||||
" stlr %w1, [%0]\n"
|
||||
: : "r" (&lock->lock), "r" (0) : "memory");
|
||||
" stlr %w1, %0\n"
|
||||
: "=Q" (lock->lock) : "r" (0) : "memory");
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -94,13 +94,13 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
|
|||
asm volatile(
|
||||
" sevl\n"
|
||||
"1: wfe\n"
|
||||
"2: ldaxr %w0, [%1]\n"
|
||||
"2: ldaxr %w0, %1\n"
|
||||
" cbnz %w0, 1b\n"
|
||||
" stxr %w0, %w2, [%1]\n"
|
||||
" stxr %w0, %w2, %1\n"
|
||||
" cbnz %w0, 2b\n"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&rw->lock), "r" (0x80000000)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "+Q" (rw->lock)
|
||||
: "r" (0x80000000)
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
static inline int arch_write_trylock(arch_rwlock_t *rw)
|
||||
|
|
@ -108,13 +108,13 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
|
|||
unsigned int tmp;
|
||||
|
||||
asm volatile(
|
||||
" ldaxr %w0, [%1]\n"
|
||||
" ldaxr %w0, %1\n"
|
||||
" cbnz %w0, 1f\n"
|
||||
" stxr %w0, %w2, [%1]\n"
|
||||
" stxr %w0, %w2, %1\n"
|
||||
"1:\n"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&rw->lock), "r" (0x80000000)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "+Q" (rw->lock)
|
||||
: "r" (0x80000000)
|
||||
: "cc", "memory");
|
||||
|
||||
return !tmp;
|
||||
}
|
||||
|
|
@ -122,8 +122,8 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
|
|||
static inline void arch_write_unlock(arch_rwlock_t *rw)
|
||||
{
|
||||
asm volatile(
|
||||
" stlr %w1, [%0]\n"
|
||||
: : "r" (&rw->lock), "r" (0) : "memory");
|
||||
" stlr %w1, %0\n"
|
||||
: "=Q" (rw->lock) : "r" (0) : "memory");
|
||||
}
|
||||
|
||||
/* write_can_lock - would write_trylock() succeed? */
|
||||
|
|
@ -148,14 +148,14 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
|
|||
asm volatile(
|
||||
" sevl\n"
|
||||
"1: wfe\n"
|
||||
"2: ldaxr %w0, [%2]\n"
|
||||
"2: ldaxr %w0, %2\n"
|
||||
" add %w0, %w0, #1\n"
|
||||
" tbnz %w0, #31, 1b\n"
|
||||
" stxr %w1, %w0, [%2]\n"
|
||||
" stxr %w1, %w0, %2\n"
|
||||
" cbnz %w1, 2b\n"
|
||||
: "=&r" (tmp), "=&r" (tmp2)
|
||||
: "r" (&rw->lock)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
|
||||
:
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
static inline void arch_read_unlock(arch_rwlock_t *rw)
|
||||
|
|
@ -163,13 +163,13 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
|
|||
unsigned int tmp, tmp2;
|
||||
|
||||
asm volatile(
|
||||
"1: ldxr %w0, [%2]\n"
|
||||
"1: ldxr %w0, %2\n"
|
||||
" sub %w0, %w0, #1\n"
|
||||
" stlxr %w1, %w0, [%2]\n"
|
||||
" stlxr %w1, %w0, %2\n"
|
||||
" cbnz %w1, 1b\n"
|
||||
: "=&r" (tmp), "=&r" (tmp2)
|
||||
: "r" (&rw->lock)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
|
||||
:
|
||||
: "cc", "memory");
|
||||
}
|
||||
|
||||
static inline int arch_read_trylock(arch_rwlock_t *rw)
|
||||
|
|
@ -177,14 +177,14 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
|
|||
unsigned int tmp, tmp2 = 1;
|
||||
|
||||
asm volatile(
|
||||
" ldaxr %w0, [%2]\n"
|
||||
" ldaxr %w0, %2\n"
|
||||
" add %w0, %w0, #1\n"
|
||||
" tbnz %w0, #31, 1f\n"
|
||||
" stxr %w1, %w0, [%2]\n"
|
||||
" stxr %w1, %w0, %2\n"
|
||||
"1:\n"
|
||||
: "=&r" (tmp), "+r" (tmp2)
|
||||
: "r" (&rw->lock)
|
||||
: "memory");
|
||||
: "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
|
||||
:
|
||||
: "cc", "memory");
|
||||
|
||||
return !tmp2;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue