sh: sh7343 Enable SDIO IRQs
This patch enables interrupt generation for SDIO IRQs of the SDHI block on the sh7343 processor. Use together with a recent SDHI driver using TMIO_MMC_SDIO_IRQ and with the MMC_CAP_SDIO_IRQ flag in the board code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -360,6 +360,8 @@ void __init plat_early_device_setup(void)
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enum {
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UNUSED = 0,
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ENABLED,
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DISABLED,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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@ -375,15 +377,13 @@ enum {
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I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
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I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
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SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
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IRDA,
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SDHI0, SDHI1, SDHI2, SDHI3,
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CMT, TSIF, SIU,
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IRDA, SDHI, CMT, TSIF, SIU,
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TMU0, TMU1, TMU2,
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JPU, LCDC,
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/* interrupt groups */
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DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
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DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
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};
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static struct intc_vect vectors[] __initdata = {
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@ -412,8 +412,8 @@ static struct intc_vect vectors[] __initdata = {
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INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
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INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
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INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
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INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
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INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
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INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
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INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
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INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
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INTC_VECT(SIU, 0xf80),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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@ -431,7 +431,6 @@ static struct intc_group groups[] __initdata = {
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INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
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INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
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INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
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INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
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INTC_GROUP(USB, USBI0, USBI1),
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};
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@ -452,7 +451,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
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{ I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
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FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
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{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
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{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
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{ DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
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{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
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{ 0, 0, 0, CMT, 0, USBI1, USBI0 } },
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{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
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@ -488,9 +487,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
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mask_registers, prio_registers, sense_registers,
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ack_registers);
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static struct intc_desc intc_desc __initdata = {
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.name = "sh7343",
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.force_enable = ENABLED,
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.force_disable = DISABLED,
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.hw = INTC_HW_DESC(vectors, groups, mask_registers,
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prio_registers, sense_registers, ack_registers),
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};
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void __init plat_irq_setup(void)
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{
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