iommu/arm-smmu: support buggy implementations with secure cfg accesses
In such a case we have to use secure aliases of some non-secure registers. This handling is switched on by DT property "calxeda,smmu-secure-config-access" for an SMMU node. Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com> [will: merged with driver option handling patch] Signed-off-by: Will Deacon <will.deacon@arm.com>hifive-unleashed-5.1
parent
636e97b0fb
commit
3a5df8ff35
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@ -60,6 +60,16 @@
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#define ARM_SMMU_GR0(smmu) ((smmu)->base)
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#define ARM_SMMU_GR0(smmu) ((smmu)->base)
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#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
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#define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
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/*
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* SMMU global address space with conditional offset to access secure
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* aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
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* nsGFSYNR0: 0x450)
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*/
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#define ARM_SMMU_GR0_NS(smmu) \
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((smmu)->base + \
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((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
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? 0x400 : 0))
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/* Page table bits */
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/* Page table bits */
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#define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
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#define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
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#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
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#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
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@ -351,6 +361,9 @@ struct arm_smmu_device {
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#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
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#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
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#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
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#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
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u32 features;
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u32 features;
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#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
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u32 options;
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int version;
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int version;
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u32 num_context_banks;
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u32 num_context_banks;
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@ -401,6 +414,29 @@ struct arm_smmu_domain {
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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
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static LIST_HEAD(arm_smmu_devices);
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static LIST_HEAD(arm_smmu_devices);
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struct arm_smmu_option_prop {
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u32 opt;
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const char *prop;
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};
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static struct arm_smmu_option_prop arm_smmu_options [] = {
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{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
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{ 0, NULL},
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};
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static void parse_driver_options(struct arm_smmu_device *smmu)
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{
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int i = 0;
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do {
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if (of_property_read_bool(smmu->dev->of_node,
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arm_smmu_options[i].prop)) {
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smmu->options |= arm_smmu_options[i].opt;
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dev_notice(smmu->dev, "option %s\n",
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arm_smmu_options[i].prop);
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}
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} while (arm_smmu_options[++i].opt);
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}
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static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
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static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
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struct device_node *dev_node)
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struct device_node *dev_node)
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{
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{
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@ -614,16 +650,16 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
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{
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{
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u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
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u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
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struct arm_smmu_device *smmu = dev;
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struct arm_smmu_device *smmu = dev;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
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gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
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gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
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if (!gfsr)
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return IRQ_NONE;
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gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
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gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
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gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
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gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
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gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
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gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
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if (!gfsr)
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return IRQ_NONE;
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dev_err_ratelimited(smmu->dev,
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dev_err_ratelimited(smmu->dev,
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"Unexpected global fault, this could be serious\n");
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"Unexpected global fault, this could be serious\n");
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dev_err_ratelimited(smmu->dev,
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dev_err_ratelimited(smmu->dev,
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@ -1597,9 +1633,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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int i = 0;
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int i = 0;
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u32 reg;
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u32 reg;
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/* Clear Global FSR */
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/* clear global FSR */
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reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
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reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
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writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR);
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writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
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/* Mark all SMRn as invalid and all S2CRn as bypass */
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/* Mark all SMRn as invalid and all S2CRn as bypass */
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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@ -1619,7 +1655,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
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reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
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reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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/* Enable fault reporting */
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/* Enable fault reporting */
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reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
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reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
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@ -1638,7 +1674,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Push the button */
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/* Push the button */
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arm_smmu_tlb_sync(smmu);
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arm_smmu_tlb_sync(smmu);
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writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0);
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writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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}
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}
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static int arm_smmu_id_size_to_bits(int size)
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static int arm_smmu_id_size_to_bits(int size)
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@ -1885,6 +1921,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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if (err)
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if (err)
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goto out_put_parent;
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goto out_put_parent;
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parse_driver_options(smmu);
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if (smmu->version > 1 &&
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if (smmu->version > 1 &&
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smmu->num_context_banks != smmu->num_context_irqs) {
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smmu->num_context_banks != smmu->num_context_irqs) {
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dev_err(dev,
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dev_err(dev,
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@ -1969,7 +2007,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev)
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free_irq(smmu->irqs[i], smmu);
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free_irq(smmu->irqs[i], smmu);
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/* Turn the thing off */
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/* Turn the thing off */
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writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
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writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
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return 0;
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return 0;
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}
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}
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