- Remove HAS_DMA config dependencies
- New STMicroelectronics STM32 IPCC driver - Enable QCom driver to run more controllers - Fixed return code from null to ptr-err for Brcm driver - Fix kconfig dependencies for the HiSilicon driver -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAlsYFY4ACgkQf9lkf8eY P5VhPQ/8DbyMaI2U5Hejj+nLSerDJgi8CfuSqEJbZF5qXktNH7neKyTIo7m3v2TK d0U900s2/kT5f57gerT5OypyBTT9tn6E2MR/WHBGqLxF/BHeKY3ftICRQRVLeICP 3btM2QRfMG0e0s0t39zib8FG7HNhV3zDHraCmgW0MizCaV2+kMuk0LlzRrPXlwah CuhbkTNCgD1R/G2TQmddfXsblTgSieBrswkzvLk9S5SedO+glO8oM2AkpYo30fqC V5YHxeY8PWA4jmkw2bXHW3vbw2p1dtwMdixDkAnBBaqz3W+oD3DLSUzYeiT6QIMx lBRMDv5/1Py/fQ4N+20oFiUC7XbTiFTWY+FBPUVckxHm5RRNN7jfceMHttqfxV6m OtVeB2pbYSZfPHZ2TqhfzzF84ZexhyfZiPgh6aI09PSaYc83yn4VBWaAwirVYnSi hSCJM/iG1QHi+4E24mYrbEkRaHqpRE7HxBR7FFsNU0BCn/1LP4oXBZQ63dDqgpa2 URAx4dCBNmzIEKtWpkuVaxkerYqJB81+oMKvFNNqjd2+vthVNNDrBxBNRgyyAUyY feSlIiIm9JBfwMPUHGc6buY7VjoC4NwJZmkbVDImDPb/aKWN4uKCgnn8R28lN/j4 ta9tZYfLjCPt3Bs1kDAQ+gCGKU9xsLwiTSoDOhCqukqirhbNhX8= =Eao7 -----END PGP SIGNATURE----- Merge tag 'mailbox-v4.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - Remove HAS_DMA config dependencies - New STMicroelectronics STM32 IPCC driver - Enable QCom driver to run more controllers - Fixed return code from null to ptr-err for Brcm driver - Fix kconfig dependencies for the HiSilicon driver * tag 'mailbox-v4.18' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox/drivers/hisi: Consolidate the Kconfig for the MAILBOX mailbox: Add support for Qualcomm SDM845 SoCs dt-bindings: mailbox: Add APSS shared binding for SDM845 SoCs mailbox: bcm2835: Fix of_xlate return value mailbox: qcom: Add msm8998 hmss compatible mailbox: add STMicroelectronics STM32 IPCC driver dt-bindings: mailbox: add STMicroelectronics STM32 IPCC binding mailbox: Remove depends on HAS_DMA in case of platform dependencyhifive-unleashed-5.1
Linus Torvalds
commit
3a979e8c07
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|
@ -10,6 +10,8 @@ platforms.
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|||
Definition: must be one of:
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"qcom,msm8916-apcs-kpss-global",
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"qcom,msm8996-apcs-hmss-global"
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"qcom,msm8998-apcs-hmss-global"
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"qcom,sdm845-apss-shared"
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- reg:
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Usage: required
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|
|
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@ -0,0 +1,47 @@
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* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
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The IPCC block provides a non blocking signaling mechanism to post and
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retrieve messages in an atomic way between two processors.
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It provides the signaling for N bidirectionnal channels. The number of channels
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(N) can be read from a dedicated register.
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Required properties:
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- compatible: Must be "st,stm32mp1-ipcc"
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- reg: Register address range (base address and length)
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- st,proc-id: Processor id using the mailbox (0 or 1)
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- clocks: Input clock
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- interrupt-names: List of names for the interrupts described by the interrupt
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property. Must contain the following entries:
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- "rx"
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- "tx"
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- "wakeup"
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- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
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free" and "system wakeup".
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- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
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The data contained in the mbox specifier of the "mboxes"
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property in the client node is the mailbox channel index.
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Optional properties:
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- wakeup-source: Flag to indicate whether this device can wake up the system
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Example:
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ipcc: mailbox@4c001000 {
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compatible = "st,stm32mp1-ipcc";
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#mbox-cells = <1>;
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reg = <0x4c001000 0x400>;
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st,proc-id = <0>;
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interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
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<&intc GIC_SPI 101 IRQ_TYPE_NONE>,
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<&aiec 62 1>;
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interrupt-names = "rx", "tx", "wakeup";
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clocks = <&rcc_clk IPCC>;
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wakeup-source;
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}
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Client:
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mbox_test {
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...
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mboxes = <&ipcc 0>, <&ipcc 1>;
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};
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@ -109,16 +109,20 @@ config TI_MESSAGE_MANAGER
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platform has support for the hardware block.
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config HI3660_MBOX
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tristate "Hi3660 Mailbox"
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depends on ARCH_HISI && OF
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tristate "Hi3660 Mailbox" if EXPERT
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depends on (ARCH_HISI || COMPILE_TEST)
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depends on OF
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default ARCH_HISI
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help
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An implementation of the hi3660 mailbox. It is used to send message
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between application processors and other processors/MCU/DSP. Select
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Y here if you want to use Hi3660 mailbox controller.
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config HI6220_MBOX
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tristate "Hi6220 Mailbox"
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depends on ARCH_HISI
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tristate "Hi6220 Mailbox" if EXPERT
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depends on (ARCH_HISI || COMPILE_TEST)
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depends on OF
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default ARCH_HISI
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help
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An implementation of the hi6220 mailbox. It is used to send message
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between application processors and MCU. Say Y here if you want to
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@ -162,7 +166,6 @@ config XGENE_SLIMPRO_MBOX
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config BCM_PDC_MBOX
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tristate "Broadcom FlexSparx DMA Mailbox"
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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depends on HAS_DMA
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help
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Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
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which provides access to various offload engines on Broadcom
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@ -172,11 +175,18 @@ config BCM_FLEXRM_MBOX
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tristate "Broadcom FlexRM Mailbox"
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depends on ARM64
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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depends on HAS_DMA
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select GENERIC_MSI_IRQ_DOMAIN
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default m if ARCH_BCM_IPROC
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help
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Mailbox implementation of the Broadcom FlexRM ring manager,
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which provides access to various offload engines on Broadcom
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SoCs. Say Y here if you want to use the Broadcom FlexRM.
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config STM32_IPCC
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tristate "STM32 IPCC Mailbox"
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depends on MACH_STM32MP157
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help
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Mailbox implementation for STMicroelectonics STM32 family chips
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with hardware for Inter-Processor Communication Controller (IPCC)
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between processors. Say Y here if you want to have this support.
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endif
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@ -38,3 +38,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
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@ -134,7 +134,7 @@ static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox,
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const struct of_phandle_args *sp)
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{
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if (sp->args_count != 0)
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return NULL;
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return ERR_PTR(-EINVAL);
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return &mbox->chans[0];
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}
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@ -125,6 +125,8 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
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static const struct of_device_id qcom_apcs_ipc_of_match[] = {
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{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
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{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
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{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
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{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
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|
|
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@ -0,0 +1,402 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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* Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#define IPCC_XCR 0x000
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#define XCR_RXOIE BIT(0)
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#define XCR_TXOIE BIT(16)
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#define IPCC_XMR 0x004
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#define IPCC_XSCR 0x008
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#define IPCC_XTOYSR 0x00c
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#define IPCC_PROC_OFFST 0x010
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#define IPCC_HWCFGR 0x3f0
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#define IPCFGR_CHAN_MASK GENMASK(7, 0)
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#define IPCC_VER 0x3f4
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#define VER_MINREV_MASK GENMASK(3, 0)
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#define VER_MAJREV_MASK GENMASK(7, 4)
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#define RX_BIT_MASK GENMASK(15, 0)
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#define RX_BIT_CHAN(chan) BIT(chan)
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#define TX_BIT_SHIFT 16
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#define TX_BIT_MASK GENMASK(31, 16)
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#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
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#define STM32_MAX_PROCS 2
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enum {
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IPCC_IRQ_RX,
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IPCC_IRQ_TX,
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IPCC_IRQ_NUM,
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};
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struct stm32_ipcc {
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struct mbox_controller controller;
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void __iomem *reg_base;
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void __iomem *reg_proc;
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struct clk *clk;
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int irqs[IPCC_IRQ_NUM];
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int wkp;
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u32 proc_id;
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u32 n_chans;
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u32 xcr;
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u32 xmr;
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};
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static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
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{
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writel_relaxed(readl_relaxed(reg) | mask, reg);
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}
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static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
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{
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writel_relaxed(readl_relaxed(reg) & ~mask, reg);
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}
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static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
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{
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struct stm32_ipcc *ipcc = data;
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struct device *dev = ipcc->controller.dev;
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u32 status, mr, tosr, chan;
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irqreturn_t ret = IRQ_NONE;
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int proc_offset;
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/* read 'channel occupied' status from other proc */
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proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
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tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
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mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
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/* search for unmasked 'channel occupied' */
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status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
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for (chan = 0; chan < ipcc->n_chans; chan++) {
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if (!(status & (1 << chan)))
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continue;
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dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
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mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
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RX_BIT_CHAN(chan));
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
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{
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struct stm32_ipcc *ipcc = data;
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struct device *dev = ipcc->controller.dev;
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u32 status, mr, tosr, chan;
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irqreturn_t ret = IRQ_NONE;
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tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
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mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
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/* search for unmasked 'channel free' */
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status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
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for (chan = 0; chan < ipcc->n_chans ; chan++) {
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if (!(status & (1 << chan)))
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continue;
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dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
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/* mask 'tx channel free' interrupt */
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stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
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TX_BIT_CHAN(chan));
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|
||||
mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
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||||
|
||||
ret = IRQ_HANDLED;
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}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
|
||||
{
|
||||
unsigned int chan = (unsigned int)link->con_priv;
|
||||
struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
|
||||
controller);
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||||
|
||||
dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
|
||||
|
||||
/* set channel n occupied */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
|
||||
|
||||
/* unmask 'tx channel free' interrupt */
|
||||
stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_ipcc_startup(struct mbox_chan *link)
|
||||
{
|
||||
unsigned int chan = (unsigned int)link->con_priv;
|
||||
struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
|
||||
controller);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(ipcc->clk);
|
||||
if (ret) {
|
||||
dev_err(ipcc->controller.dev, "can not enable the clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* unmask 'rx channel occupied' interrupt */
|
||||
stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stm32_ipcc_shutdown(struct mbox_chan *link)
|
||||
{
|
||||
unsigned int chan = (unsigned int)link->con_priv;
|
||||
struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
|
||||
controller);
|
||||
|
||||
/* mask rx/tx interrupt */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
|
||||
RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
|
||||
|
||||
clk_disable_unprepare(ipcc->clk);
|
||||
}
|
||||
|
||||
static const struct mbox_chan_ops stm32_ipcc_ops = {
|
||||
.send_data = stm32_ipcc_send_data,
|
||||
.startup = stm32_ipcc_startup,
|
||||
.shutdown = stm32_ipcc_shutdown,
|
||||
};
|
||||
|
||||
static int stm32_ipcc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct stm32_ipcc *ipcc;
|
||||
struct resource *res;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
u32 ip_ver;
|
||||
static const char * const irq_name[] = {"rx", "tx"};
|
||||
irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};
|
||||
|
||||
if (!np) {
|
||||
dev_err(dev, "No DT found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
|
||||
if (!ipcc)
|
||||
return -ENOMEM;
|
||||
|
||||
/* proc_id */
|
||||
if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
|
||||
dev_err(dev, "Missing st,proc-id\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (ipcc->proc_id >= STM32_MAX_PROCS) {
|
||||
dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* regs */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ipcc->reg_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(ipcc->reg_base))
|
||||
return PTR_ERR(ipcc->reg_base);
|
||||
|
||||
ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
|
||||
|
||||
/* clock */
|
||||
ipcc->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(ipcc->clk))
|
||||
return PTR_ERR(ipcc->clk);
|
||||
|
||||
ret = clk_prepare_enable(ipcc->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can not enable the clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* irq */
|
||||
for (i = 0; i < IPCC_IRQ_NUM; i++) {
|
||||
ipcc->irqs[i] = of_irq_get_byname(dev->of_node, irq_name[i]);
|
||||
if (ipcc->irqs[i] < 0) {
|
||||
dev_err(dev, "no IRQ specified %s\n", irq_name[i]);
|
||||
ret = ipcc->irqs[i];
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
|
||||
irq_thread[i], IRQF_ONESHOT,
|
||||
dev_name(dev), ipcc);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq %d (%d)\n", i, ret);
|
||||
goto err_clk;
|
||||
}
|
||||
}
|
||||
|
||||
/* mask and enable rx/tx irq */
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
|
||||
RX_BIT_MASK | TX_BIT_MASK);
|
||||
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);
|
||||
|
||||
/* wakeup */
|
||||
if (of_property_read_bool(np, "wakeup-source")) {
|
||||
ipcc->wkp = of_irq_get_byname(dev->of_node, "wakeup");
|
||||
if (ipcc->wkp < 0) {
|
||||
dev_err(dev, "could not get wakeup IRQ\n");
|
||||
ret = ipcc->wkp;
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
device_init_wakeup(dev, true);
|
||||
ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to set wake up irq\n");
|
||||
goto err_init_wkp;
|
||||
}
|
||||
} else {
|
||||
device_init_wakeup(dev, false);
|
||||
}
|
||||
|
||||
/* mailbox controller */
|
||||
ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
|
||||
ipcc->n_chans &= IPCFGR_CHAN_MASK;
|
||||
|
||||
ipcc->controller.dev = dev;
|
||||
ipcc->controller.txdone_irq = true;
|
||||
ipcc->controller.ops = &stm32_ipcc_ops;
|
||||
ipcc->controller.num_chans = ipcc->n_chans;
|
||||
ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
|
||||
sizeof(*ipcc->controller.chans),
|
||||
GFP_KERNEL);
|
||||
if (!ipcc->controller.chans) {
|
||||
ret = -ENOMEM;
|
||||
goto err_irq_wkp;
|
||||
}
|
||||
|
||||
for (i = 0; i < ipcc->controller.num_chans; i++)
|
||||
ipcc->controller.chans[i].con_priv = (void *)i;
|
||||
|
||||
ret = mbox_controller_register(&ipcc->controller);
|
||||
if (ret)
|
||||
goto err_irq_wkp;
|
||||
|
||||
platform_set_drvdata(pdev, ipcc);
|
||||
|
||||
ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
|
||||
|
||||
dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
|
||||
FIELD_GET(VER_MAJREV_MASK, ip_ver),
|
||||
FIELD_GET(VER_MINREV_MASK, ip_ver),
|
||||
ipcc->controller.num_chans, ipcc->proc_id);
|
||||
|
||||
clk_disable_unprepare(ipcc->clk);
|
||||
return 0;
|
||||
|
||||
err_irq_wkp:
|
||||
if (ipcc->wkp)
|
||||
dev_pm_clear_wake_irq(dev);
|
||||
err_init_wkp:
|
||||
device_init_wakeup(dev, false);
|
||||
err_clk:
|
||||
clk_disable_unprepare(ipcc->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_ipcc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
|
||||
|
||||
mbox_controller_unregister(&ipcc->controller);
|
||||
|
||||
if (ipcc->wkp)
|
||||
dev_pm_clear_wake_irq(&pdev->dev);
|
||||
|
||||
device_init_wakeup(&pdev->dev, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
|
||||
{
|
||||
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
|
||||
unsigned int i;
|
||||
|
||||
if (device_may_wakeup(dev))
|
||||
for (i = 0; i < IPCC_IRQ_NUM; i++)
|
||||
irq_set_irq_wake(ipcc->irqs[i], enable);
|
||||
}
|
||||
|
||||
static int stm32_ipcc_suspend(struct device *dev)
|
||||
{
|
||||
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
|
||||
|
||||
ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
|
||||
ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
|
||||
|
||||
stm32_ipcc_set_irq_wake(dev, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_ipcc_resume(struct device *dev)
|
||||
{
|
||||
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
|
||||
|
||||
stm32_ipcc_set_irq_wake(dev, false);
|
||||
|
||||
writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
|
||||
writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
|
||||
stm32_ipcc_suspend, stm32_ipcc_resume);
|
||||
|
||||
static const struct of_device_id stm32_ipcc_of_match[] = {
|
||||
{ .compatible = "st,stm32mp1-ipcc" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);
|
||||
|
||||
static struct platform_driver stm32_ipcc_driver = {
|
||||
.driver = {
|
||||
.name = "stm32-ipcc",
|
||||
.pm = &stm32_ipcc_pm_ops,
|
||||
.of_match_table = stm32_ipcc_of_match,
|
||||
},
|
||||
.probe = stm32_ipcc_probe,
|
||||
.remove = stm32_ipcc_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(stm32_ipcc_driver);
|
||||
|
||||
MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
|
||||
MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
|
||||
MODULE_DESCRIPTION("STM32 IPCC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue