drm/i915: Move hangcheck code out from i915_irq.c
Create new file for hangcheck specific code, intel_hangcheck.c, and move all related code in it. v2: s/intel_engine_hangcheck/intel_engine (Chris) No functional changes. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1478018583-5816-1-git-send-email-mika.kuoppala@intel.comhifive-unleashed-5.1
parent
fce937559e
commit
3ac168a70b
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@ -47,6 +47,7 @@ i915-y += i915_cmd_parser.o \
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i915_trace_points.o \
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intel_breadcrumbs.o \
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intel_engine_cs.o \
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intel_hangcheck.o \
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intel_lrc.o \
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intel_mocs.o \
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intel_ringbuffer.o \
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@ -830,6 +830,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
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intel_init_dpio(dev_priv);
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intel_power_domains_init(dev_priv);
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intel_irq_init(dev_priv);
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intel_hangcheck_init(dev_priv);
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intel_init_display_hooks(dev_priv);
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intel_init_clock_gating_hooks(dev_priv);
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intel_init_audio_hooks(dev_priv);
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@ -3009,6 +3009,7 @@ extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
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extern void i915_reset(struct drm_i915_private *dev_priv);
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extern int intel_guc_reset(struct drm_i915_private *dev_priv);
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extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
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extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
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extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
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extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
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extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
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@ -2848,420 +2848,6 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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static bool
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ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
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{
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if (INTEL_GEN(engine->i915) >= 8) {
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return (ipehr >> 23) == 0x1c;
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} else {
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ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
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return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
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MI_SEMAPHORE_REGISTER);
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}
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}
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static struct intel_engine_cs *
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semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
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u64 offset)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_engine_cs *signaller;
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enum intel_engine_id id;
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if (INTEL_GEN(dev_priv) >= 8) {
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for_each_engine(signaller, dev_priv, id) {
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if (engine == signaller)
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continue;
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if (offset == signaller->semaphore.signal_ggtt[engine->hw_id])
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return signaller;
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}
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} else {
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u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
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for_each_engine(signaller, dev_priv, id) {
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if(engine == signaller)
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continue;
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if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id])
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return signaller;
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}
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}
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DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x, offset 0x%016llx\n",
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engine->name, ipehr, offset);
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return ERR_PTR(-ENODEV);
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}
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static struct intel_engine_cs *
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semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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void __iomem *vaddr;
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u32 cmd, ipehr, head;
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u64 offset = 0;
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int i, backwards;
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/*
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* This function does not support execlist mode - any attempt to
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* proceed further into this function will result in a kernel panic
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* when dereferencing ring->buffer, which is not set up in execlist
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* mode.
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*
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* The correct way of doing it would be to derive the currently
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* executing ring buffer from the current context, which is derived
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* from the currently running request. Unfortunately, to get the
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* current request we would have to grab the struct_mutex before doing
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* anything else, which would be ill-advised since some other thread
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* might have grabbed it already and managed to hang itself, causing
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* the hang checker to deadlock.
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*
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* Therefore, this function does not support execlist mode in its
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* current form. Just return NULL and move on.
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*/
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if (engine->buffer == NULL)
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return NULL;
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ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
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if (!ipehr_is_semaphore_wait(engine, ipehr))
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return NULL;
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/*
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* HEAD is likely pointing to the dword after the actual command,
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* so scan backwards until we find the MBOX. But limit it to just 3
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* or 4 dwords depending on the semaphore wait command size.
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* Note that we don't care about ACTHD here since that might
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* point at at batch, and semaphores are always emitted into the
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* ringbuffer itself.
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*/
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head = I915_READ_HEAD(engine) & HEAD_ADDR;
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backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
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vaddr = (void __iomem *)engine->buffer->vaddr;
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for (i = backwards; i; --i) {
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/*
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* Be paranoid and presume the hw has gone off into the wild -
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* our ring is smaller than what the hardware (and hence
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* HEAD_ADDR) allows. Also handles wrap-around.
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*/
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head &= engine->buffer->size - 1;
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/* This here seems to blow up */
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cmd = ioread32(vaddr + head);
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if (cmd == ipehr)
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break;
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head -= 4;
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}
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if (!i)
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return NULL;
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*seqno = ioread32(vaddr + head + 4) + 1;
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if (INTEL_GEN(dev_priv) >= 8) {
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offset = ioread32(vaddr + head + 12);
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offset <<= 32;
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offset |= ioread32(vaddr + head + 8);
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}
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return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
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}
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static int semaphore_passed(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_engine_cs *signaller;
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u32 seqno;
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engine->hangcheck.deadlock++;
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signaller = semaphore_waits_for(engine, &seqno);
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if (signaller == NULL)
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return -1;
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if (IS_ERR(signaller))
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return 0;
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/* Prevent pathological recursion due to driver bugs */
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if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
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return -1;
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if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
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return 1;
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/* cursory check for an unkickable deadlock */
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if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
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semaphore_passed(signaller) < 0)
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return -1;
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return 0;
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}
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static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine(engine, dev_priv, id)
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engine->hangcheck.deadlock = 0;
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}
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static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
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{
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u32 tmp = current_instdone | *old_instdone;
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bool unchanged;
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unchanged = tmp == *old_instdone;
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*old_instdone |= tmp;
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return unchanged;
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}
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static bool subunits_stuck(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_instdone instdone;
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struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
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bool stuck;
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int slice;
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int subslice;
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if (engine->id != RCS)
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return true;
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intel_engine_get_instdone(engine, &instdone);
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/* There might be unstable subunit states even when
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* actual head is not moving. Filter out the unstable ones by
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* accumulating the undone -> done transitions and only
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* consider those as progress.
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*/
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stuck = instdone_unchanged(instdone.instdone,
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&accu_instdone->instdone);
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stuck &= instdone_unchanged(instdone.slice_common,
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&accu_instdone->slice_common);
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for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
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stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
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&accu_instdone->sampler[slice][subslice]);
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stuck &= instdone_unchanged(instdone.row[slice][subslice],
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&accu_instdone->row[slice][subslice]);
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}
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return stuck;
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}
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static enum intel_engine_hangcheck_action
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head_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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if (acthd != engine->hangcheck.acthd) {
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/* Clear subunit states on head movement */
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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return HANGCHECK_ACTIVE;
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}
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if (!subunits_stuck(engine))
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return HANGCHECK_ACTIVE;
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return HANGCHECK_HUNG;
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}
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static enum intel_engine_hangcheck_action
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engine_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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enum intel_engine_hangcheck_action ha;
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u32 tmp;
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ha = head_stuck(engine, acthd);
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if (ha != HANGCHECK_HUNG)
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return ha;
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if (IS_GEN2(dev_priv))
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return HANGCHECK_HUNG;
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/* Is the chip hanging on a WAIT_FOR_EVENT?
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* If so we can simply poke the RB_WAIT bit
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* and break the hang. This should work on
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* all but the second generation chipsets.
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*/
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tmp = I915_READ_CTL(engine);
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if (tmp & RING_WAIT) {
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i915_handle_error(dev_priv, 0,
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"Kicking stuck wait on %s",
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engine->name);
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I915_WRITE_CTL(engine, tmp);
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return HANGCHECK_KICK;
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}
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if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
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switch (semaphore_passed(engine)) {
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default:
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return HANGCHECK_HUNG;
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case 1:
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i915_handle_error(dev_priv, 0,
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"Kicking stuck semaphore on %s",
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engine->name);
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I915_WRITE_CTL(engine, tmp);
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return HANGCHECK_KICK;
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case 0:
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return HANGCHECK_WAIT;
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}
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}
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return HANGCHECK_HUNG;
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}
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/*
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* This is called when the chip hasn't reported back with completed
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* batchbuffers in a long time. We keep track per ring seqno progress and
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* if there are no progress, hangcheck score for that ring is increased.
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* Further, acthd is inspected to see if the ring is stuck. On stuck case
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* we kick the ring. If we see no progress on three subsequent calls
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* we assume chip is wedged and try to fix it by resetting the chip.
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*/
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static void i915_hangcheck_elapsed(struct work_struct *work)
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{
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struct drm_i915_private *dev_priv =
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container_of(work, typeof(*dev_priv),
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gpu_error.hangcheck_work.work);
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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unsigned int hung = 0, stuck = 0;
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int busy_count = 0;
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#define BUSY 1
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#define KICK 5
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#define HUNG 20
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#define ACTIVE_DECAY 15
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if (!i915.enable_hangcheck)
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return;
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if (!READ_ONCE(dev_priv->gt.awake))
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return;
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/* As enabling the GPU requires fairly extensive mmio access,
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* periodically arm the mmio checker to see if we are triggering
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* any invalid access.
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*/
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intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
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for_each_engine(engine, dev_priv, id) {
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bool busy = intel_engine_has_waiter(engine);
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u64 acthd;
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u32 seqno;
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u32 submit;
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semaphore_clear_deadlocks(dev_priv);
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/* We don't strictly need an irq-barrier here, as we are not
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* serving an interrupt request, be paranoid in case the
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* barrier has side-effects (such as preventing a broken
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* cacheline snoop) and so be sure that we can see the seqno
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* advance. If the seqno should stick, due to a stale
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* cacheline, we would erroneously declare the GPU hung.
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*/
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if (engine->irq_seqno_barrier)
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engine->irq_seqno_barrier(engine);
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acthd = intel_engine_get_active_head(engine);
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seqno = intel_engine_get_seqno(engine);
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submit = intel_engine_last_submit(engine);
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if (engine->hangcheck.seqno == seqno) {
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if (i915_seqno_passed(seqno, submit)) {
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engine->hangcheck.action = HANGCHECK_IDLE;
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} else {
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/* We always increment the hangcheck score
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* if the engine is busy and still processing
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* the same request, so that no single request
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* can run indefinitely (such as a chain of
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* batches). The only time we do not increment
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* the hangcheck score on this ring, if this
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* engine is in a legitimate wait for another
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* engine. In that case the waiting engine is a
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* victim and we want to be sure we catch the
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* right culprit. Then every time we do kick
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* the ring, add a small increment to the
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* score so that we can catch a batch that is
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* being repeatedly kicked and so responsible
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* for stalling the machine.
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*/
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engine->hangcheck.action =
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engine_stuck(engine, acthd);
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switch (engine->hangcheck.action) {
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case HANGCHECK_IDLE:
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case HANGCHECK_WAIT:
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break;
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case HANGCHECK_ACTIVE:
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engine->hangcheck.score += BUSY;
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break;
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case HANGCHECK_KICK:
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engine->hangcheck.score += KICK;
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break;
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case HANGCHECK_HUNG:
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engine->hangcheck.score += HUNG;
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break;
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}
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}
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if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
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hung |= intel_engine_flag(engine);
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if (engine->hangcheck.action != HANGCHECK_HUNG)
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stuck |= intel_engine_flag(engine);
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}
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} else {
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engine->hangcheck.action = HANGCHECK_ACTIVE;
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/* Gradually reduce the count so that we catch DoS
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* attempts across multiple batches.
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*/
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if (engine->hangcheck.score > 0)
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engine->hangcheck.score -= ACTIVE_DECAY;
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if (engine->hangcheck.score < 0)
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engine->hangcheck.score = 0;
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/* Clear head and subunit states on seqno movement */
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acthd = 0;
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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}
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engine->hangcheck.seqno = seqno;
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engine->hangcheck.acthd = acthd;
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busy_count += busy;
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}
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if (hung) {
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char msg[80];
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unsigned int tmp;
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int len;
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/* If some rings hung but others were still busy, only
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* blame the hanging rings in the synopsis.
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*/
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if (stuck != hung)
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hung &= ~stuck;
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len = scnprintf(msg, sizeof(msg),
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"%s on ", stuck == hung ? "No progress" : "Hang");
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for_each_engine_masked(engine, dev_priv, hung, tmp)
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len += scnprintf(msg + len, sizeof(msg) - len,
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"%s, ", engine->name);
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msg[len-2] = '\0';
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return i915_handle_error(dev_priv, hung, msg);
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}
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/* Reset timer in case GPU hangs without another request being added */
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if (busy_count)
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i915_queue_hangcheck(dev_priv);
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}
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static void ibx_irq_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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@ -4583,9 +4169,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
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if (INTEL_INFO(dev_priv)->gen >= 8)
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dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
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INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
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i915_hangcheck_elapsed);
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if (IS_GEN2(dev_priv)) {
|
||||
/* Gen2 doesn't have a hardware frame counter */
|
||||
dev->max_vblank_count = 0;
|
||||
|
|
|
@ -220,11 +220,6 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
|
|||
intel_engine_wakeup(engine);
|
||||
}
|
||||
|
||||
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
|
||||
{
|
||||
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
|
||||
}
|
||||
|
||||
static void intel_engine_init_timeline(struct intel_engine_cs *engine)
|
||||
{
|
||||
engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
|
||||
|
|
|
@ -0,0 +1,450 @@
|
|||
/*
|
||||
* Copyright © 2016 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "i915_drv.h"
|
||||
|
||||
static bool
|
||||
ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
|
||||
{
|
||||
if (INTEL_GEN(engine->i915) >= 8) {
|
||||
return (ipehr >> 23) == 0x1c;
|
||||
} else {
|
||||
ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
|
||||
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
|
||||
MI_SEMAPHORE_REGISTER);
|
||||
}
|
||||
}
|
||||
|
||||
static struct intel_engine_cs *
|
||||
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
|
||||
u64 offset)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
struct intel_engine_cs *signaller;
|
||||
enum intel_engine_id id;
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 8) {
|
||||
for_each_engine(signaller, dev_priv, id) {
|
||||
if (engine == signaller)
|
||||
continue;
|
||||
|
||||
if (offset == signaller->semaphore.signal_ggtt[engine->hw_id])
|
||||
return signaller;
|
||||
}
|
||||
} else {
|
||||
u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
|
||||
|
||||
for_each_engine(signaller, dev_priv, id) {
|
||||
if(engine == signaller)
|
||||
continue;
|
||||
|
||||
if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id])
|
||||
return signaller;
|
||||
}
|
||||
}
|
||||
|
||||
DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x, offset 0x%016llx\n",
|
||||
engine->name, ipehr, offset);
|
||||
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
static struct intel_engine_cs *
|
||||
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
void __iomem *vaddr;
|
||||
u32 cmd, ipehr, head;
|
||||
u64 offset = 0;
|
||||
int i, backwards;
|
||||
|
||||
/*
|
||||
* This function does not support execlist mode - any attempt to
|
||||
* proceed further into this function will result in a kernel panic
|
||||
* when dereferencing ring->buffer, which is not set up in execlist
|
||||
* mode.
|
||||
*
|
||||
* The correct way of doing it would be to derive the currently
|
||||
* executing ring buffer from the current context, which is derived
|
||||
* from the currently running request. Unfortunately, to get the
|
||||
* current request we would have to grab the struct_mutex before doing
|
||||
* anything else, which would be ill-advised since some other thread
|
||||
* might have grabbed it already and managed to hang itself, causing
|
||||
* the hang checker to deadlock.
|
||||
*
|
||||
* Therefore, this function does not support execlist mode in its
|
||||
* current form. Just return NULL and move on.
|
||||
*/
|
||||
if (engine->buffer == NULL)
|
||||
return NULL;
|
||||
|
||||
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
|
||||
if (!ipehr_is_semaphore_wait(engine, ipehr))
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
* HEAD is likely pointing to the dword after the actual command,
|
||||
* so scan backwards until we find the MBOX. But limit it to just 3
|
||||
* or 4 dwords depending on the semaphore wait command size.
|
||||
* Note that we don't care about ACTHD here since that might
|
||||
* point at at batch, and semaphores are always emitted into the
|
||||
* ringbuffer itself.
|
||||
*/
|
||||
head = I915_READ_HEAD(engine) & HEAD_ADDR;
|
||||
backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
|
||||
vaddr = (void __iomem *)engine->buffer->vaddr;
|
||||
|
||||
for (i = backwards; i; --i) {
|
||||
/*
|
||||
* Be paranoid and presume the hw has gone off into the wild -
|
||||
* our ring is smaller than what the hardware (and hence
|
||||
* HEAD_ADDR) allows. Also handles wrap-around.
|
||||
*/
|
||||
head &= engine->buffer->size - 1;
|
||||
|
||||
/* This here seems to blow up */
|
||||
cmd = ioread32(vaddr + head);
|
||||
if (cmd == ipehr)
|
||||
break;
|
||||
|
||||
head -= 4;
|
||||
}
|
||||
|
||||
if (!i)
|
||||
return NULL;
|
||||
|
||||
*seqno = ioread32(vaddr + head + 4) + 1;
|
||||
if (INTEL_GEN(dev_priv) >= 8) {
|
||||
offset = ioread32(vaddr + head + 12);
|
||||
offset <<= 32;
|
||||
offset |= ioread32(vaddr + head + 8);
|
||||
}
|
||||
return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
|
||||
}
|
||||
|
||||
static int semaphore_passed(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
struct intel_engine_cs *signaller;
|
||||
u32 seqno;
|
||||
|
||||
engine->hangcheck.deadlock++;
|
||||
|
||||
signaller = semaphore_waits_for(engine, &seqno);
|
||||
if (signaller == NULL)
|
||||
return -1;
|
||||
|
||||
if (IS_ERR(signaller))
|
||||
return 0;
|
||||
|
||||
/* Prevent pathological recursion due to driver bugs */
|
||||
if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
|
||||
return -1;
|
||||
|
||||
if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
|
||||
return 1;
|
||||
|
||||
/* cursory check for an unkickable deadlock */
|
||||
if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
|
||||
semaphore_passed(signaller) < 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_engine_cs *engine;
|
||||
enum intel_engine_id id;
|
||||
|
||||
for_each_engine(engine, dev_priv, id)
|
||||
engine->hangcheck.deadlock = 0;
|
||||
}
|
||||
|
||||
static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
|
||||
{
|
||||
u32 tmp = current_instdone | *old_instdone;
|
||||
bool unchanged;
|
||||
|
||||
unchanged = tmp == *old_instdone;
|
||||
*old_instdone |= tmp;
|
||||
|
||||
return unchanged;
|
||||
}
|
||||
|
||||
static bool subunits_stuck(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
struct intel_instdone instdone;
|
||||
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
|
||||
bool stuck;
|
||||
int slice;
|
||||
int subslice;
|
||||
|
||||
if (engine->id != RCS)
|
||||
return true;
|
||||
|
||||
intel_engine_get_instdone(engine, &instdone);
|
||||
|
||||
/* There might be unstable subunit states even when
|
||||
* actual head is not moving. Filter out the unstable ones by
|
||||
* accumulating the undone -> done transitions and only
|
||||
* consider those as progress.
|
||||
*/
|
||||
stuck = instdone_unchanged(instdone.instdone,
|
||||
&accu_instdone->instdone);
|
||||
stuck &= instdone_unchanged(instdone.slice_common,
|
||||
&accu_instdone->slice_common);
|
||||
|
||||
for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
|
||||
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
|
||||
&accu_instdone->sampler[slice][subslice]);
|
||||
stuck &= instdone_unchanged(instdone.row[slice][subslice],
|
||||
&accu_instdone->row[slice][subslice]);
|
||||
}
|
||||
|
||||
return stuck;
|
||||
}
|
||||
|
||||
static enum intel_engine_hangcheck_action
|
||||
head_stuck(struct intel_engine_cs *engine, u64 acthd)
|
||||
{
|
||||
if (acthd != engine->hangcheck.acthd) {
|
||||
|
||||
/* Clear subunit states on head movement */
|
||||
memset(&engine->hangcheck.instdone, 0,
|
||||
sizeof(engine->hangcheck.instdone));
|
||||
|
||||
return HANGCHECK_ACTIVE;
|
||||
}
|
||||
|
||||
if (!subunits_stuck(engine))
|
||||
return HANGCHECK_ACTIVE;
|
||||
|
||||
return HANGCHECK_HUNG;
|
||||
}
|
||||
|
||||
static enum intel_engine_hangcheck_action
|
||||
engine_stuck(struct intel_engine_cs *engine, u64 acthd)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
enum intel_engine_hangcheck_action ha;
|
||||
u32 tmp;
|
||||
|
||||
ha = head_stuck(engine, acthd);
|
||||
if (ha != HANGCHECK_HUNG)
|
||||
return ha;
|
||||
|
||||
if (IS_GEN2(dev_priv))
|
||||
return HANGCHECK_HUNG;
|
||||
|
||||
/* Is the chip hanging on a WAIT_FOR_EVENT?
|
||||
* If so we can simply poke the RB_WAIT bit
|
||||
* and break the hang. This should work on
|
||||
* all but the second generation chipsets.
|
||||
*/
|
||||
tmp = I915_READ_CTL(engine);
|
||||
if (tmp & RING_WAIT) {
|
||||
i915_handle_error(dev_priv, 0,
|
||||
"Kicking stuck wait on %s",
|
||||
engine->name);
|
||||
I915_WRITE_CTL(engine, tmp);
|
||||
return HANGCHECK_KICK;
|
||||
}
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
|
||||
switch (semaphore_passed(engine)) {
|
||||
default:
|
||||
return HANGCHECK_HUNG;
|
||||
case 1:
|
||||
i915_handle_error(dev_priv, 0,
|
||||
"Kicking stuck semaphore on %s",
|
||||
engine->name);
|
||||
I915_WRITE_CTL(engine, tmp);
|
||||
return HANGCHECK_KICK;
|
||||
case 0:
|
||||
return HANGCHECK_WAIT;
|
||||
}
|
||||
}
|
||||
|
||||
return HANGCHECK_HUNG;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is called when the chip hasn't reported back with completed
|
||||
* batchbuffers in a long time. We keep track per ring seqno progress and
|
||||
* if there are no progress, hangcheck score for that ring is increased.
|
||||
* Further, acthd is inspected to see if the ring is stuck. On stuck case
|
||||
* we kick the ring. If we see no progress on three subsequent calls
|
||||
* we assume chip is wedged and try to fix it by resetting the chip.
|
||||
*/
|
||||
static void i915_hangcheck_elapsed(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, typeof(*dev_priv),
|
||||
gpu_error.hangcheck_work.work);
|
||||
struct intel_engine_cs *engine;
|
||||
enum intel_engine_id id;
|
||||
unsigned int hung = 0, stuck = 0;
|
||||
int busy_count = 0;
|
||||
#define BUSY 1
|
||||
#define KICK 5
|
||||
#define HUNG 20
|
||||
#define ACTIVE_DECAY 15
|
||||
|
||||
if (!i915.enable_hangcheck)
|
||||
return;
|
||||
|
||||
if (!READ_ONCE(dev_priv->gt.awake))
|
||||
return;
|
||||
|
||||
/* As enabling the GPU requires fairly extensive mmio access,
|
||||
* periodically arm the mmio checker to see if we are triggering
|
||||
* any invalid access.
|
||||
*/
|
||||
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
|
||||
|
||||
for_each_engine(engine, dev_priv, id) {
|
||||
bool busy = intel_engine_has_waiter(engine);
|
||||
u64 acthd;
|
||||
u32 seqno;
|
||||
u32 submit;
|
||||
|
||||
semaphore_clear_deadlocks(dev_priv);
|
||||
|
||||
/* We don't strictly need an irq-barrier here, as we are not
|
||||
* serving an interrupt request, be paranoid in case the
|
||||
* barrier has side-effects (such as preventing a broken
|
||||
* cacheline snoop) and so be sure that we can see the seqno
|
||||
* advance. If the seqno should stick, due to a stale
|
||||
* cacheline, we would erroneously declare the GPU hung.
|
||||
*/
|
||||
if (engine->irq_seqno_barrier)
|
||||
engine->irq_seqno_barrier(engine);
|
||||
|
||||
acthd = intel_engine_get_active_head(engine);
|
||||
seqno = intel_engine_get_seqno(engine);
|
||||
submit = intel_engine_last_submit(engine);
|
||||
|
||||
if (engine->hangcheck.seqno == seqno) {
|
||||
if (i915_seqno_passed(seqno, submit)) {
|
||||
engine->hangcheck.action = HANGCHECK_IDLE;
|
||||
} else {
|
||||
/* We always increment the hangcheck score
|
||||
* if the engine is busy and still processing
|
||||
* the same request, so that no single request
|
||||
* can run indefinitely (such as a chain of
|
||||
* batches). The only time we do not increment
|
||||
* the hangcheck score on this ring, if this
|
||||
* engine is in a legitimate wait for another
|
||||
* engine. In that case the waiting engine is a
|
||||
* victim and we want to be sure we catch the
|
||||
* right culprit. Then every time we do kick
|
||||
* the ring, add a small increment to the
|
||||
* score so that we can catch a batch that is
|
||||
* being repeatedly kicked and so responsible
|
||||
* for stalling the machine.
|
||||
*/
|
||||
engine->hangcheck.action =
|
||||
engine_stuck(engine, acthd);
|
||||
|
||||
switch (engine->hangcheck.action) {
|
||||
case HANGCHECK_IDLE:
|
||||
case HANGCHECK_WAIT:
|
||||
break;
|
||||
case HANGCHECK_ACTIVE:
|
||||
engine->hangcheck.score += BUSY;
|
||||
break;
|
||||
case HANGCHECK_KICK:
|
||||
engine->hangcheck.score += KICK;
|
||||
break;
|
||||
case HANGCHECK_HUNG:
|
||||
engine->hangcheck.score += HUNG;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
|
||||
hung |= intel_engine_flag(engine);
|
||||
if (engine->hangcheck.action != HANGCHECK_HUNG)
|
||||
stuck |= intel_engine_flag(engine);
|
||||
}
|
||||
} else {
|
||||
engine->hangcheck.action = HANGCHECK_ACTIVE;
|
||||
|
||||
/* Gradually reduce the count so that we catch DoS
|
||||
* attempts across multiple batches.
|
||||
*/
|
||||
if (engine->hangcheck.score > 0)
|
||||
engine->hangcheck.score -= ACTIVE_DECAY;
|
||||
if (engine->hangcheck.score < 0)
|
||||
engine->hangcheck.score = 0;
|
||||
|
||||
/* Clear head and subunit states on seqno movement */
|
||||
acthd = 0;
|
||||
|
||||
memset(&engine->hangcheck.instdone, 0,
|
||||
sizeof(engine->hangcheck.instdone));
|
||||
}
|
||||
|
||||
engine->hangcheck.seqno = seqno;
|
||||
engine->hangcheck.acthd = acthd;
|
||||
busy_count += busy;
|
||||
}
|
||||
|
||||
if (hung) {
|
||||
char msg[80];
|
||||
unsigned int tmp;
|
||||
int len;
|
||||
|
||||
/* If some rings hung but others were still busy, only
|
||||
* blame the hanging rings in the synopsis.
|
||||
*/
|
||||
if (stuck != hung)
|
||||
hung &= ~stuck;
|
||||
len = scnprintf(msg, sizeof(msg),
|
||||
"%s on ", stuck == hung ? "No progress" : "Hang");
|
||||
for_each_engine_masked(engine, dev_priv, hung, tmp)
|
||||
len += scnprintf(msg + len, sizeof(msg) - len,
|
||||
"%s, ", engine->name);
|
||||
msg[len-2] = '\0';
|
||||
|
||||
return i915_handle_error(dev_priv, hung, msg);
|
||||
}
|
||||
|
||||
/* Reset timer in case GPU hangs without another request being added */
|
||||
if (busy_count)
|
||||
i915_queue_hangcheck(dev_priv);
|
||||
}
|
||||
|
||||
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
|
||||
{
|
||||
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
|
||||
}
|
||||
|
||||
void intel_hangcheck_init(struct drm_i915_private *i915)
|
||||
{
|
||||
INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
|
||||
i915_hangcheck_elapsed);
|
||||
}
|
Loading…
Reference in New Issue