drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -245,7 +245,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
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/*
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* TLB invalidate requires a post-sync write.
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*/
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flags |= PIPE_CONTROL_QW_WRITE;
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flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
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}
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ret = intel_ring_begin(ring, 4);
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