ath9k: Separate routines for PCOEM and SoC calibration
Though there is some overlap between the calibration mechanisms of PC-OEM cards and SoC chip families, dumping both of them into a single function makes things hard to understand. ar9003_hw_init_cal() is unreadable with chip-specific segments scattered around. To make the logic understandable, use different functions for client cards and SoC chips. Some code is duplicated, but in the long run, it makes the code more maintanable. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1040,7 +1040,195 @@ static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
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}
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}
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static bool ar9003_hw_init_cal(struct ath_hw *ah,
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static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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bool txiqcal_done = false;
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bool is_reusable = true, status = true;
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bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
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bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
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u32 rx_delay = 0;
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u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
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AR_PHY_AGC_CONTROL_FLTR_CAL |
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AR_PHY_AGC_CONTROL_PKDET_CAL;
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/* Use chip chainmask only for calibration */
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ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
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if (rtt) {
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if (!ar9003_hw_rtt_restore(ah, chan))
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run_rtt_cal = true;
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if (run_rtt_cal)
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ath_dbg(common, CALIBRATE, "RTT calibration to be done\n");
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}
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run_agc_cal = run_rtt_cal;
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if (run_rtt_cal) {
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ar9003_hw_rtt_enable(ah);
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ar9003_hw_rtt_set_mask(ah, 0x00);
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ar9003_hw_rtt_clear_hist(ah);
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}
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if (rtt) {
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if (!run_rtt_cal) {
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agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
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agc_supp_cals &= agc_ctrl;
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agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
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AR_PHY_AGC_CONTROL_FLTR_CAL |
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AR_PHY_AGC_CONTROL_PKDET_CAL);
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REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
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} else {
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if (ah->ah_flags & AH_FASTCC)
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run_agc_cal = true;
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}
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}
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if (ah->enabled_cals & TX_CL_CAL) {
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if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
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REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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else {
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REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
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AR_PHY_CL_CAL_ENABLE);
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run_agc_cal = true;
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}
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}
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if ((IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) ||
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!(ah->enabled_cals & TX_IQ_CAL))
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goto skip_tx_iqcal;
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/* Do Tx IQ Calibration */
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REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
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AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
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DELPT);
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/*
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* For AR9485 or later chips, TxIQ cal runs as part of
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* AGC calibration
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*/
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if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
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if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
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REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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else
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REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
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txiqcal_done = run_agc_cal = true;
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} else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
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run_agc_cal = true;
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sep_iq_cal = true;
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}
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skip_tx_iqcal:
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if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
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ar9003_mci_init_cal_req(ah, &is_reusable);
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if (sep_iq_cal) {
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txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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udelay(5);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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}
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if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
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rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
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/* Disable BB_active */
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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udelay(5);
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REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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}
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if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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AR_PHY_AGC_CONTROL_CAL);
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/* Poll for offset calibration complete */
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status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_CAL,
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0, AH_WAIT_TIMEOUT);
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ar9003_hw_do_manual_peak_cal(ah, chan, run_rtt_cal);
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}
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if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
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REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
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udelay(5);
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}
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if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
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ar9003_mci_init_cal_done(ah);
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if (rtt && !run_rtt_cal) {
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agc_ctrl |= agc_supp_cals;
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REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
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}
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if (!status) {
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if (run_rtt_cal)
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ar9003_hw_rtt_disable(ah);
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ath_dbg(common, CALIBRATE,
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"offset calibration failed to complete in %d ms; noisy environment?\n",
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AH_WAIT_TIMEOUT / 1000);
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return false;
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}
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if (txiqcal_done)
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ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
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else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
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ar9003_hw_tx_iq_cal_reload(ah);
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ar9003_hw_cl_cal_post_proc(ah, is_reusable);
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if (run_rtt_cal && caldata) {
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if (is_reusable) {
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if (!ath9k_hw_rfbus_req(ah)) {
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ath_err(ath9k_hw_common(ah),
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"Could not stop baseband\n");
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} else {
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ar9003_hw_rtt_fill_hist(ah);
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if (test_bit(SW_PKDET_DONE, &caldata->cal_flags))
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ar9003_hw_rtt_load_hist(ah);
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}
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ath9k_hw_rfbus_done(ah);
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}
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ar9003_hw_rtt_disable(ah);
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}
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/* Revert chainmask to runtime parameters */
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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/* Initialize list pointers */
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ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
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INIT_CAL(&ah->iq_caldata);
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INSERT_CAL(ah, &ah->iq_caldata);
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ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
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/* Initialize current pointer to first element in list */
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ah->cal_list_curr = ah->cal_list;
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if (ah->cal_list_curr)
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ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
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if (caldata)
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caldata->CalValid = 0;
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return true;
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}
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static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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@ -1233,8 +1421,12 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
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priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
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else
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priv_ops->init_cal = ar9003_hw_init_cal_soc;
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priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
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priv_ops->init_cal = ar9003_hw_init_cal;
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priv_ops->setup_calibration = ar9003_hw_setup_calibration;
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ops->calibrate = ar9003_hw_calibrate;
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