IB/mlx5: Support device memory type attribute
This patch intoruduces a new mlx5_ib driver attribute to the DM allocation method - the DM type. In order to allow addition of new types in downstream patches this patch also refactors the allocation, deallocation and registration handlers to consider the requested type and perform the necessary actions according to it. Since not all future device memory types will be such that are mapped to user memory, the mandatory page index output attribute is modified to be optional. Signed-off-by: Ariel Levkovich <lariel@mellanox.com> Reviewed-by: Eli Cohen <eli@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>hifive-unleashed-5.2
Ariel Levkovich
Jason Gunthorpe
parent
3a4ef2e2b5
commit
3b113a1ec3
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@ -82,10 +82,10 @@ int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *dev,
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return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out));
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}
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int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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u64 length, u32 alignment)
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int mlx5_cmd_alloc_memic(struct mlx5_dm *dm, phys_addr_t *addr,
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u64 length, u32 alignment)
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{
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struct mlx5_core_dev *dev = memic->dev;
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struct mlx5_core_dev *dev = dm->dev;
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u64 num_memic_hw_pages = MLX5_CAP_DEV_MEM(dev, memic_bar_size)
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>> PAGE_SHIFT;
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u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
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@ -115,17 +115,17 @@ int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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mlx5_alignment);
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while (page_idx < num_memic_hw_pages) {
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spin_lock(&memic->memic_lock);
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page_idx = bitmap_find_next_zero_area(memic->memic_alloc_pages,
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spin_lock(&dm->lock);
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page_idx = bitmap_find_next_zero_area(dm->memic_alloc_pages,
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num_memic_hw_pages,
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page_idx,
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num_pages, 0);
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if (page_idx < num_memic_hw_pages)
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bitmap_set(memic->memic_alloc_pages,
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bitmap_set(dm->memic_alloc_pages,
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page_idx, num_pages);
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spin_unlock(&memic->memic_lock);
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spin_unlock(&dm->lock);
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if (page_idx >= num_memic_hw_pages)
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break;
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@ -135,10 +135,10 @@ int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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if (ret) {
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spin_lock(&memic->memic_lock);
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bitmap_clear(memic->memic_alloc_pages,
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spin_lock(&dm->lock);
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bitmap_clear(dm->memic_alloc_pages,
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page_idx, num_pages);
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spin_unlock(&memic->memic_lock);
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spin_unlock(&dm->lock);
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if (ret == -EAGAIN) {
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page_idx++;
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@ -157,9 +157,9 @@ int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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return -ENOMEM;
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}
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int mlx5_cmd_dealloc_memic(struct mlx5_memic *memic, u64 addr, u64 length)
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int mlx5_cmd_dealloc_memic(struct mlx5_dm *dm, u64 addr, u64 length)
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{
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struct mlx5_core_dev *dev = memic->dev;
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struct mlx5_core_dev *dev = dm->dev;
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u64 hw_start_addr = MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr);
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u32 num_pages = DIV_ROUND_UP(length, PAGE_SIZE);
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u32 out[MLX5_ST_SZ_DW(dealloc_memic_out)] = {0};
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@ -177,10 +177,10 @@ int mlx5_cmd_dealloc_memic(struct mlx5_memic *memic, u64 addr, u64 length)
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err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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if (!err) {
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spin_lock(&memic->memic_lock);
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bitmap_clear(memic->memic_alloc_pages,
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spin_lock(&dm->lock);
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bitmap_clear(dm->memic_alloc_pages,
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start_page_idx, num_pages);
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spin_unlock(&memic->memic_lock);
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spin_unlock(&dm->lock);
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}
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return err;
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@ -44,9 +44,9 @@ int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point,
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int mlx5_cmd_query_ext_ppcnt_counters(struct mlx5_core_dev *dev, void *out);
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int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *mdev,
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void *in, int in_size);
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int mlx5_cmd_alloc_memic(struct mlx5_memic *memic, phys_addr_t *addr,
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int mlx5_cmd_alloc_memic(struct mlx5_dm *dm, phys_addr_t *addr,
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u64 length, u32 alignment);
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int mlx5_cmd_dealloc_memic(struct mlx5_memic *memic, u64 addr, u64 length);
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int mlx5_cmd_dealloc_memic(struct mlx5_dm *dm, u64 addr, u64 length);
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void mlx5_cmd_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid);
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void mlx5_cmd_destroy_tir(struct mlx5_core_dev *dev, u32 tirn, u16 uid);
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void mlx5_cmd_destroy_tis(struct mlx5_core_dev *dev, u32 tisn, u16 uid);
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@ -2264,58 +2264,90 @@ static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vm
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return 0;
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}
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struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
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struct ib_ucontext *context,
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struct ib_dm_alloc_attr *attr,
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struct uverbs_attr_bundle *attrs)
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static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
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struct mlx5_ib_dm *dm,
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struct ib_dm_alloc_attr *attr,
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struct uverbs_attr_bundle *attrs)
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{
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u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
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struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
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phys_addr_t memic_addr;
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struct mlx5_ib_dm *dm;
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struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
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u64 start_offset;
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u32 page_idx;
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int err;
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dm = kzalloc(sizeof(*dm), GFP_KERNEL);
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if (!dm)
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return ERR_PTR(-ENOMEM);
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dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
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mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
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attr->length, act_size, attr->alignment);
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err = mlx5_cmd_alloc_memic(memic, &memic_addr,
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act_size, attr->alignment);
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err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
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dm->size, attr->alignment);
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if (err)
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goto err_free;
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return err;
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start_offset = memic_addr & ~PAGE_MASK;
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page_idx = (memic_addr - memic->dev->bar_addr -
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MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
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page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
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MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
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PAGE_SHIFT;
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err = uverbs_copy_to(attrs,
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MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
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&start_offset, sizeof(start_offset));
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if (err)
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goto err_dealloc;
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err = uverbs_copy_to(attrs,
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MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
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&page_idx, sizeof(page_idx));
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if (err)
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goto err_dealloc;
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bitmap_set(to_mucontext(context)->dm_pages, page_idx,
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DIV_ROUND_UP(act_size, PAGE_SIZE));
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start_offset = dm->dev_addr & ~PAGE_MASK;
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err = uverbs_copy_to(attrs,
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MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
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&start_offset, sizeof(start_offset));
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if (err)
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goto err_dealloc;
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dm->dev_addr = memic_addr;
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bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
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DIV_ROUND_UP(dm->size, PAGE_SIZE));
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return 0;
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err_dealloc:
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mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
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return err;
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}
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struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
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struct ib_ucontext *context,
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struct ib_dm_alloc_attr *attr,
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struct uverbs_attr_bundle *attrs)
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{
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struct mlx5_ib_dm *dm;
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enum mlx5_ib_uapi_dm_type type;
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int err;
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err = uverbs_get_const_default(&type, attrs,
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MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
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MLX5_IB_UAPI_DM_TYPE_MEMIC);
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if (err)
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return ERR_PTR(err);
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mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
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type, attr->length, attr->alignment);
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dm = kzalloc(sizeof(*dm), GFP_KERNEL);
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if (!dm)
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return ERR_PTR(-ENOMEM);
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dm->type = type;
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switch (type) {
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case MLX5_IB_UAPI_DM_TYPE_MEMIC:
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err = handle_alloc_dm_memic(context, dm,
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attr,
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attrs);
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break;
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default:
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err = -EOPNOTSUPP;
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}
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if (err)
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goto err_free;
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return &dm->ibdm;
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err_dealloc:
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mlx5_cmd_dealloc_memic(memic, memic_addr,
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act_size);
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err_free:
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kfree(dm);
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return ERR_PTR(err);
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@ -2323,25 +2355,31 @@ err_free:
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int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
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{
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struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
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struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
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struct mlx5_ib_dm *dm = to_mdm(ibdm);
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u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
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u32 page_idx;
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int ret;
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ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
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if (ret)
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return ret;
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switch (dm->type) {
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case MLX5_IB_UAPI_DM_TYPE_MEMIC:
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ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
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if (ret)
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return ret;
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page_idx = (dm->dev_addr - memic->dev->bar_addr -
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MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
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PAGE_SHIFT;
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bitmap_clear(rdma_udata_to_drv_context(
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&attrs->driver_udata,
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struct mlx5_ib_ucontext,
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ibucontext)->dm_pages,
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page_idx,
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DIV_ROUND_UP(act_size, PAGE_SIZE));
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page_idx = (dm->dev_addr -
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pci_resource_start(dm_db->dev->pdev, 0) -
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MLX5_CAP64_DEV_MEM(dm_db->dev,
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memic_bar_start_addr)) >>
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PAGE_SHIFT;
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bitmap_clear(rdma_udata_to_drv_context(&attrs->driver_udata,
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struct mlx5_ib_ucontext,
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ibucontext)
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->dm_pages,
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page_idx, DIV_ROUND_UP(dm->size, PAGE_SIZE));
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break;
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default:
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return -EOPNOTSUPP;
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}
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kfree(dm);
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@ -5768,7 +5806,10 @@ ADD_UVERBS_ATTRIBUTES_SIMPLE(
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UA_MANDATORY),
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UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
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UVERBS_ATTR_TYPE(u16),
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UA_MANDATORY));
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UA_OPTIONAL),
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UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
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enum mlx5_ib_uapi_dm_type,
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UA_OPTIONAL));
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ADD_UVERBS_ATTRIBUTES_SIMPLE(
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mlx5_ib_flow_action,
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@ -5916,8 +5957,8 @@ static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
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INIT_LIST_HEAD(&dev->qp_list);
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spin_lock_init(&dev->reset_flow_resource_lock);
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spin_lock_init(&dev->memic.memic_lock);
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dev->memic.dev = mdev;
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spin_lock_init(&dev->dm.lock);
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dev->dm.dev = mdev;
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if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
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err = init_srcu_struct(&dev->mr_srcu);
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@ -48,6 +48,7 @@
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#include <rdma/mlx5-abi.h>
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#include <rdma/uverbs_ioctl.h>
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#include <rdma/mlx5_user_ioctl_cmds.h>
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#include <rdma/mlx5_user_ioctl_verbs.h>
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#include "srq.h"
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@ -554,15 +555,17 @@ enum mlx5_ib_mtt_access_flags {
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struct mlx5_ib_dm {
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struct ib_dm ibdm;
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phys_addr_t dev_addr;
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u32 type;
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size_t size;
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};
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#define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
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#define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
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IB_ACCESS_REMOTE_WRITE |\
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IB_ACCESS_REMOTE_READ |\
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IB_ACCESS_REMOTE_ATOMIC |\
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IB_ZERO_BASED)
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#define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
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IB_ACCESS_REMOTE_WRITE |\
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IB_ACCESS_REMOTE_READ |\
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IB_ACCESS_REMOTE_ATOMIC |\
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IB_ZERO_BASED)
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struct mlx5_ib_mr {
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struct ib_mr ibmr;
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@ -843,9 +846,13 @@ struct mlx5_ib_flow_action {
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};
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};
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struct mlx5_memic {
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struct mlx5_dm {
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struct mlx5_core_dev *dev;
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spinlock_t memic_lock;
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/* This lock is used to protect the access to the shared
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* allocation map when concurrent requests by different
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* processes are handled.
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*/
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spinlock_t lock;
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DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
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};
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@ -949,7 +956,7 @@ struct mlx5_ib_dev {
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u8 umr_fence;
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struct list_head ib_dev_list;
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u64 sys_image_guid;
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struct mlx5_memic memic;
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struct mlx5_dm dm;
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u16 devx_whitelist_uid;
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struct mlx5_srq_table srq_table;
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struct mlx5_async_ctx async_ctx;
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@ -1159,8 +1159,8 @@ static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
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mr->access_flags = access_flags;
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}
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static struct ib_mr *mlx5_ib_get_memic_mr(struct ib_pd *pd, u64 memic_addr,
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u64 length, int acc)
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static struct ib_mr *mlx5_ib_get_dm_mr(struct ib_pd *pd, u64 start_addr,
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u64 length, int acc, int mode)
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{
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struct mlx5_ib_dev *dev = to_mdev(pd->device);
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int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
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@ -1182,9 +1182,8 @@ static struct ib_mr *mlx5_ib_get_memic_mr(struct ib_pd *pd, u64 memic_addr,
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mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
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MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MEMIC & 0x3);
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MLX5_SET(mkc, mkc, access_mode_4_2,
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(MLX5_MKC_ACCESS_MODE_MEMIC >> 2) & 0x7);
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MLX5_SET(mkc, mkc, access_mode_1_0, mode & 0x3);
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MLX5_SET(mkc, mkc, access_mode_4_2, (mode >> 2) & 0x7);
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MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
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MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
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MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
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@ -1194,7 +1193,7 @@ static struct ib_mr *mlx5_ib_get_memic_mr(struct ib_pd *pd, u64 memic_addr,
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MLX5_SET64(mkc, mkc, len, length);
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MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
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MLX5_SET(mkc, mkc, qpn, 0xffffff);
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MLX5_SET64(mkc, mkc, start_addr, memic_addr - dev->mdev->bar_addr);
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MLX5_SET64(mkc, mkc, start_addr, start_addr);
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err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
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if (err)
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@ -1236,15 +1235,24 @@ struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
|
|||
struct uverbs_attr_bundle *attrs)
|
||||
{
|
||||
struct mlx5_ib_dm *mdm = to_mdm(dm);
|
||||
u64 memic_addr;
|
||||
struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev;
|
||||
u64 start_addr = mdm->dev_addr + attr->offset;
|
||||
int mode;
|
||||
|
||||
if (attr->access_flags & ~MLX5_IB_DM_ALLOWED_ACCESS)
|
||||
switch (mdm->type) {
|
||||
case MLX5_IB_UAPI_DM_TYPE_MEMIC:
|
||||
if (attr->access_flags & ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
mode = MLX5_MKC_ACCESS_MODE_MEMIC;
|
||||
start_addr -= pci_resource_start(dev->pdev, 0);
|
||||
break;
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
memic_addr = mdm->dev_addr + attr->offset;
|
||||
|
||||
return mlx5_ib_get_memic_mr(pd, memic_addr, attr->length,
|
||||
attr->access_flags);
|
||||
return mlx5_ib_get_dm_mr(pd, start_addr, attr->length,
|
||||
attr->access_flags, mode);
|
||||
}
|
||||
|
||||
struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ enum mlx5_ib_create_flow_action_attrs {
|
|||
enum mlx5_ib_alloc_dm_attrs {
|
||||
MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET = (1U << UVERBS_ID_NS_SHIFT),
|
||||
MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
|
||||
MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
|
||||
};
|
||||
|
||||
enum mlx5_ib_devx_methods {
|
||||
|
|
|
|||
|
|
@ -57,5 +57,9 @@ struct mlx5_ib_uapi_devx_async_cmd_hdr {
|
|||
__u8 out_data[];
|
||||
};
|
||||
|
||||
enum mlx5_ib_uapi_dm_type {
|
||||
MLX5_IB_UAPI_DM_TYPE_MEMIC,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue