drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions. Additionally, the ICL DSI encoder needs to do the clock gating and ungating slightly differently, and this allows its own handling in a clean fashion. Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f8e2982ceea4c05dc254a0c15e2b3be1d5f271d3.1543500285.git.jani.nikula@intel.com
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@ -2791,69 +2791,45 @@ uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
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return 0;
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}
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void icl_map_plls_to_ports(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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struct drm_atomic_state *old_state)
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static void icl_map_plls_to_ports(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct drm_connector_state *conn_state;
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struct drm_connector *conn;
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int i;
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enum port port = encoder->port;
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u32 val;
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for_each_new_connector_in_state(old_state, conn, conn_state, i) {
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struct intel_encoder *encoder =
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to_intel_encoder(conn_state->best_encoder);
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enum port port;
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uint32_t val;
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mutex_lock(&dev_priv->dpll_lock);
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if (conn_state->crtc != crtc)
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continue;
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val = I915_READ(DPCLKA_CFGCR0_ICL);
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WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
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port = encoder->port;
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mutex_lock(&dev_priv->dpll_lock);
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val = I915_READ(DPCLKA_CFGCR0_ICL);
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WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
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if (intel_port_is_combophy(dev_priv, port)) {
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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POSTING_READ(DPCLKA_CFGCR0_ICL);
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}
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val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
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if (intel_port_is_combophy(dev_priv, port)) {
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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mutex_unlock(&dev_priv->dpll_lock);
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POSTING_READ(DPCLKA_CFGCR0_ICL);
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}
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val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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mutex_unlock(&dev_priv->dpll_lock);
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}
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void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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struct drm_atomic_state *old_state)
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static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->dev);
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struct drm_connector_state *old_conn_state;
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struct drm_connector *conn;
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int i;
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = encoder->port;
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u32 val;
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for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
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struct intel_encoder *encoder =
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to_intel_encoder(old_conn_state->best_encoder);
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enum port port;
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mutex_lock(&dev_priv->dpll_lock);
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if (old_conn_state->crtc != crtc)
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continue;
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val = I915_READ(DPCLKA_CFGCR0_ICL);
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val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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port = encoder->port;
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mutex_lock(&dev_priv->dpll_lock);
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I915_WRITE(DPCLKA_CFGCR0_ICL,
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I915_READ(DPCLKA_CFGCR0_ICL) |
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icl_dpclka_cfgcr0_clk_off(dev_priv, port));
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mutex_unlock(&dev_priv->dpll_lock);
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}
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mutex_unlock(&dev_priv->dpll_lock);
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}
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void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
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@ -3268,6 +3244,9 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
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WARN_ON(crtc_state->has_pch_encoder);
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if (INTEL_GEN(dev_priv) >= 11)
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icl_map_plls_to_ports(encoder, crtc_state);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
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@ -3370,6 +3349,8 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state,
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const struct drm_connector_state *old_conn_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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/*
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* When called from DP MST code:
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* - old_conn_state will be NULL
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@ -3389,6 +3370,9 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder,
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else
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intel_ddi_post_disable_dp(encoder,
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old_crtc_state, old_conn_state);
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if (INTEL_GEN(dev_priv) >= 11)
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icl_unmap_plls_to_ports(encoder);
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}
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void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
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@ -5726,9 +5726,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
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if (pipe_config->shared_dpll)
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intel_enable_shared_dpll(pipe_config);
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if (INTEL_GEN(dev_priv) >= 11)
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icl_map_plls_to_ports(crtc, pipe_config, old_state);
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intel_encoders_pre_enable(crtc, pipe_config, old_state);
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if (intel_crtc_has_dp_encoder(pipe_config))
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@ -5932,9 +5929,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
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intel_encoders_post_disable(crtc, old_crtc_state, old_state);
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if (INTEL_GEN(dev_priv) >= 11)
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icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
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intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
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}
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@ -1534,12 +1534,6 @@ u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
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u8 voltage_swing);
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int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
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bool enable);
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void icl_map_plls_to_ports(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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struct drm_atomic_state *old_state);
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void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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struct drm_atomic_state *old_state);
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void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
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unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
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