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x86 gart: factor out common code 

Cleanup gart handling on amd64 a bit: move common code into
enable_gart_translation , and use symbolic register names where
appropriate.

Signed-off-by: Pavel Machek <pavel@suse.cz>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
hifive-unleashed-5.1
Pavel Machek 2008-04-15 12:43:57 +02:00 committed by Ingo Molnar
parent 330fce23da
commit 3bb6fbf996
3 changed files with 32 additions and 37 deletions
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23
arch/x86/kernel/pci-gart_64.c
View File

@ -533,8 +533,8 @@ static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
unsigned aper_size = 0, aper_base_32, aper_order;
u64 aper_base;
pci_read_config_dword(dev, 0x94, &aper_base_32);
pci_read_config_dword(dev, 0x90, &aper_order);
pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
aper_order = (aper_order >> 1) & 7;
aper_base = aper_base_32 & 0x7fff;
@ -592,19 +592,8 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
agp_gatt_table = gatt;
for (i = 0; i < num_k8_northbridges; i++) {
u32 gatt_reg;
u32 ctl;
dev = k8_northbridges[i];
gatt_reg = __pa(gatt) >> 12;
gatt_reg <<= 4;
pci_write_config_dword(dev, AMD64_GARTTABLEBASE, gatt_reg);
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
ctl |= GARTEN;
ctl &= ~(DISGARTCPU | DISGARTIO);
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
enable_gart_translation(dev, __pa(gatt));
}
flush_gart();
@ -648,11 +637,11 @@ void gart_iommu_shutdown(void)
u32 ctl;
dev = k8_northbridges[i];
pci_read_config_dword(dev, 0x90, &ctl);
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
ctl &= ~1;
ctl &= ~GARTEN;
pci_write_config_dword(dev, 0x90, ctl);
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
}
}

29
drivers/char/agp/amd64-agp.c
View File

@ -150,25 +150,14 @@ static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
{
u64 aperturebase;
u32 tmp;
u64 addr, aper_base;
u64 aper_base;
/* Address to map to */
pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
aperturebase = tmp << 25;
aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
/* address of the mappings table */
addr = (u64) gatt_table;
addr >>= 12;
tmp = (u32) addr<<4;
tmp &= ~0xf;
pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp);
/* Enable GART translation for this hammer. */
pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
tmp |= GARTEN;
tmp &= ~(DISGARTCPU | DISGARTIO);
pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
enable_gart_translation(hammer, gatt_table);
return aper_base;
}
@ -207,9 +196,9 @@ static void amd64_cleanup(void)
for (i = 0; i < num_k8_northbridges; i++) {
struct pci_dev *dev = k8_northbridges[i];
/* disable gart translation */
pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
tmp &= ~AMD64_GARTEN;
pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
}
}
@ -289,9 +278,9 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
u32 nb_order, nb_base;
u16 apsize;
pci_read_config_dword(nb, 0x90, &nb_order);
pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
nb_order = (nb_order >> 1) & 7;
pci_read_config_dword(nb, 0x94, &nb_base);
pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
nb_aper = nb_base << 25;
if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
return 0;
@ -327,8 +316,8 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
return -1;
pci_write_config_dword(nb, 0x90, order << 1);
pci_write_config_dword(nb, 0x94, aper >> 25);
pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
return 0;
}

17
include/asm-x86/gart.h
View File

@ -52,4 +52,21 @@ static inline void gart_iommu_shutdown(void)
#define AMD64_GARTCACHECTL 0x9c
#define AMD64_GARTEN (1<<0)
static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
{
u32 tmp, ctl;
/* address of the mappings table */
addr >>= 12;
tmp = (u32) addr<<4;
tmp &= ~0xf;
pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
/* Enable GART translation for this hammer. */
pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
ctl |= GARTEN;
ctl &= ~(DISGARTCPU | DISGARTIO);
pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
}
#endif