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irqchip: irq-imx-gpcv2: fix the suspend/resume on imx8mq 

The wakeup irq info need to be provided to ATF side, then
ATF side can config the correct wakeup IRQ when entering
suspend.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Jacky Bai 2019-08-28 15:11:42 +08:00 committed by Dong Aisheng
parent cdcad70321
commit 3bc3ffbe14
1 changed files with 8 additions and 0 deletions
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8
drivers/irqchip/irq-imx-gpcv2.c
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@ -16,6 +16,7 @@
#include <linux/cpuidle.h>
#define FSL_SIP_GPC 0xC2000000
#define FSL_SIP_CONFIG_GPC_SET_WAKE 0x02
#define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05
#define IMR_NUM 4
@ -125,6 +126,7 @@ static void imx_gpcv2_wake_request_fixup(void)
static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct gpcv2_irqchip_data *cd = d->chip_data;
struct arm_smccc_res res;
unsigned int idx = d->hwirq / 32;
unsigned long flags;
u32 mask, val;
@ -134,8 +136,14 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
val = cd->wakeup_sources[idx];
cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
#ifdef CONFIG_ARM64
arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_SET_WAKE,
d->hwirq, on, 0, 0, 0, 0, &res);
#endif
raw_spin_unlock_irqrestore(&cd->rlock, flags);
/*
* Do *not* call into the parent, as the GIC doesn't have any
* wake-up facility...