drm/msm/adreno: push dump/show stuff to base class
Add ptr to list of interesting registers to 'struct adreno_gpu' and use that to move most of the debugfs show and register dump bits down into adreno_gpu. This will avoid duplication as support for additional adreno generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -385,58 +385,26 @@ static const unsigned int a3xx_registers[] = {
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0x2750, 0x2756, 0x2760, 0x2760, 0x300c, 0x300e, 0x301c, 0x301d,
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0x2750, 0x2756, 0x2760, 0x2760, 0x300c, 0x300e, 0x301c, 0x301d,
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0x302a, 0x302a, 0x302c, 0x302d, 0x3030, 0x3031, 0x3034, 0x3036,
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0x302a, 0x302a, 0x302c, 0x302d, 0x3030, 0x3031, 0x3034, 0x3036,
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0x303c, 0x303c, 0x305e, 0x305f,
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0x303c, 0x303c, 0x305e, 0x305f,
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~0 /* sentinel */
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};
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};
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#ifdef CONFIG_DEBUG_FS
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#ifdef CONFIG_DEBUG_FS
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static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m)
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static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m)
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{
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{
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int i;
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adreno_show(gpu, m);
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gpu->funcs->pm_resume(gpu);
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gpu->funcs->pm_resume(gpu);
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seq_printf(m, "status: %08x\n",
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seq_printf(m, "status: %08x\n",
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gpu_read(gpu, REG_A3XX_RBBM_STATUS));
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gpu_read(gpu, REG_A3XX_RBBM_STATUS));
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/* dump these out in a form that can be parsed by demsm: */
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seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; i < ARRAY_SIZE(a3xx_registers); i += 2) {
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uint32_t start = a3xx_registers[i];
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uint32_t end = a3xx_registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
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}
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}
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gpu->funcs->pm_suspend(gpu);
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gpu->funcs->pm_suspend(gpu);
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adreno_show(gpu, m);
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}
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}
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#endif
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#endif
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/* would be nice to not have to duplicate the _show() stuff with printk(): */
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/* would be nice to not have to duplicate the _show() stuff with printk(): */
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static void a3xx_dump(struct msm_gpu *gpu)
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static void a3xx_dump(struct msm_gpu *gpu)
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{
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{
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int i;
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adreno_dump(gpu);
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printk("status: %08x\n",
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printk("status: %08x\n",
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gpu_read(gpu, REG_A3XX_RBBM_STATUS));
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gpu_read(gpu, REG_A3XX_RBBM_STATUS));
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adreno_dump(gpu);
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/* dump these out in a form that can be parsed by demsm: */
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printk("IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; i < ARRAY_SIZE(a3xx_registers); i += 2) {
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uint32_t start = a3xx_registers[i];
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uint32_t end = a3xx_registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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printk("IO:R %08x %08x\n", addr<<2, val);
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}
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}
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}
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}
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static const struct adreno_gpu_funcs funcs = {
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static const struct adreno_gpu_funcs funcs = {
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@ -494,6 +462,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
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gpu->perfcntrs = perfcntrs;
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gpu->perfcntrs = perfcntrs;
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gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
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gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
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adreno_gpu->registers = a3xx_registers;
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ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
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ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
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if (ret)
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if (ret)
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goto fail;
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goto fail;
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@ -212,6 +212,7 @@ void adreno_idle(struct msm_gpu *gpu)
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void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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{
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int i;
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seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
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seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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@ -223,6 +224,23 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr);
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seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr);
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seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
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seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
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seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
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seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
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gpu->funcs->pm_resume(gpu);
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/* dump these out in a form that can be parsed by demsm: */
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seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
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uint32_t start = adreno_gpu->registers[i];
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uint32_t end = adreno_gpu->registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
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}
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}
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gpu->funcs->pm_suspend(gpu);
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}
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}
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#endif
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#endif
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@ -230,6 +248,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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void adreno_dump(struct msm_gpu *gpu)
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void adreno_dump(struct msm_gpu *gpu)
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{
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int i;
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printk("revision: %d (%d.%d.%d.%d)\n",
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printk("revision: %d (%d.%d.%d.%d)\n",
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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adreno_gpu->info->revn, adreno_gpu->rev.core,
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@ -242,6 +261,18 @@ void adreno_dump(struct msm_gpu *gpu)
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printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
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printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
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printk("rb wptr: %d\n", get_wptr(gpu->rb));
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printk("rb wptr: %d\n", get_wptr(gpu->rb));
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/* dump these out in a form that can be parsed by demsm: */
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printk("IO:region %s 00000000 00020000\n", gpu->name);
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for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
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uint32_t start = adreno_gpu->registers[i];
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uint32_t end = adreno_gpu->registers[i+1];
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uint32_t addr;
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for (addr = start; addr <= end; addr++) {
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uint32_t val = gpu_read(gpu, addr);
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printk("IO:R %08x %08x\n", addr<<2, val);
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}
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}
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}
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}
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static uint32_t ring_freewords(struct msm_gpu *gpu)
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static uint32_t ring_freewords(struct msm_gpu *gpu)
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@ -64,6 +64,9 @@ struct adreno_gpu {
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uint32_t revn; /* numeric revision name */
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uint32_t revn; /* numeric revision name */
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const struct adreno_gpu_funcs *funcs;
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const struct adreno_gpu_funcs *funcs;
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/* interesting register offsets to dump: */
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const unsigned int *registers;
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/* firmware: */
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/* firmware: */
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const struct firmware *pm4, *pfp;
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const struct firmware *pm4, *pfp;
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