net: mvpp2: add RXQ flow control configurations
This patch adds RXQ flow control configurations. Flow control disabled by default. Minimum ring size limited to 1024 descriptors. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Stefan Chulski
David S. Miller
parent
a59d354208
commit
3bd17fdc08
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@ -765,9 +765,36 @@
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/* MSS Flow control */
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#define MSS_FC_COM_REG 0
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#define FLOW_CONTROL_ENABLE_BIT BIT(0)
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#define FLOW_CONTROL_UPDATE_COMMAND_BIT BIT(31)
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#define FC_QUANTA 0xFFFF
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#define FC_CLK_DIVIDER 100
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#define MSS_THRESHOLD_STOP 768
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#define MSS_RXQ_TRESH_BASE 0x200
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#define MSS_RXQ_TRESH_OFFS 4
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#define MSS_RXQ_TRESH_REG(q, fq) (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
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* MSS_RXQ_TRESH_OFFS))
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#define MSS_RXQ_TRESH_START_MASK 0xFFFF
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#define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
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#define MSS_RXQ_TRESH_STOP_OFFS 16
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#define MSS_RXQ_ASS_BASE 0x80
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#define MSS_RXQ_ASS_OFFS 4
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#define MSS_RXQ_ASS_PER_REG 4
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#define MSS_RXQ_ASS_PER_OFFS 8
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#define MSS_RXQ_ASS_PORTID_OFFS 0
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#define MSS_RXQ_ASS_PORTID_MASK 0x3
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#define MSS_RXQ_ASS_HOSTID_OFFS 2
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#define MSS_RXQ_ASS_HOSTID_MASK 0x3F
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#define MSS_RXQ_ASS_Q_BASE(q, fq) ((((q) + (fq)) % MSS_RXQ_ASS_PER_REG) \
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* MSS_RXQ_ASS_PER_OFFS)
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#define MSS_RXQ_ASS_PQ_BASE(q, fq) ((((q) + (fq)) / MSS_RXQ_ASS_PER_REG) \
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* MSS_RXQ_ASS_OFFS)
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#define MSS_RXQ_ASS_REG(q, fq) (MSS_RXQ_ASS_BASE + MSS_RXQ_ASS_PQ_BASE(q, fq))
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#define MSS_THRESHOLD_STOP 768
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#define MSS_THRESHOLD_START 1024
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/* RX buffer constants */
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#define MVPP2_SKB_SHINFO_SIZE \
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@ -1022,6 +1049,9 @@ struct mvpp2 {
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/* Global TX Flow Control config */
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bool global_tx_fc;
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/* Spinlocks for CM3 shared memory configuration */
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spinlock_t mss_spinlock;
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};
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struct mvpp2_pcpu_stats {
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@ -1184,6 +1214,9 @@ struct mvpp2_port {
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bool rx_hwtstamp;
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enum hwtstamp_tx_types tx_hwtstamp_type;
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struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
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/* Firmware TX flow control */
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bool tx_fc;
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};
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/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
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@ -741,6 +741,110 @@ static void *mvpp2_buf_alloc(struct mvpp2_port *port,
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return data;
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}
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/* Routine enable flow control for RXQs condition */
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static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
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{
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int val, cm3_state, host_id, q;
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int fq = port->first_rxq;
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unsigned long flags;
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spin_lock_irqsave(&port->priv->mss_spinlock, flags);
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/* Remove Flow control enable bit to prevent race between FW and Kernel
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* If Flow control was enabled, it would be re-enabled.
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*/
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val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
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cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
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val &= ~FLOW_CONTROL_ENABLE_BIT;
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mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
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/* Set same Flow control for all RXQs */
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for (q = 0; q < port->nrxqs; q++) {
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/* Set stop and start Flow control RXQ thresholds */
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val = MSS_THRESHOLD_START;
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val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
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mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
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val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
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/* Set RXQ port ID */
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val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
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val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
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val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
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+ MSS_RXQ_ASS_HOSTID_OFFS));
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/* Calculate RXQ host ID:
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* In Single queue mode: Host ID equal to Host ID used for
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* shared RX interrupt
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* In Multi queue mode: Host ID equal to number of
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* RXQ ID / number of CoS queues
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* In Single resource mode: Host ID always equal to 0
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*/
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if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
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host_id = port->nqvecs;
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else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
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host_id = q;
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else
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host_id = 0;
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/* Set RXQ host ID */
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val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
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+ MSS_RXQ_ASS_HOSTID_OFFS));
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mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
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}
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/* Notify Firmware that Flow control config space ready for update */
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val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
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val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
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val |= cm3_state;
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mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
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spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
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}
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/* Routine disable flow control for RXQs condition */
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static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
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{
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int val, cm3_state, q;
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unsigned long flags;
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int fq = port->first_rxq;
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spin_lock_irqsave(&port->priv->mss_spinlock, flags);
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/* Remove Flow control enable bit to prevent race between FW and Kernel
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* If Flow control was enabled, it would be re-enabled.
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*/
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val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
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cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
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val &= ~FLOW_CONTROL_ENABLE_BIT;
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mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
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/* Disable Flow control for all RXQs */
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for (q = 0; q < port->nrxqs; q++) {
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/* Set threshold 0 to disable Flow control */
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val = 0;
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val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
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mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
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val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
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val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
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val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
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+ MSS_RXQ_ASS_HOSTID_OFFS));
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mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
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}
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/* Notify Firmware that Flow control config space ready for update */
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val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
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val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
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val |= cm3_state;
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mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
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spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
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}
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/* Release buffer to BM */
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static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
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dma_addr_t buf_dma_addr,
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@ -3013,6 +3117,9 @@ static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
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for (queue = 0; queue < port->nrxqs; queue++)
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mvpp2_rxq_deinit(port, port->rxqs[queue]);
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if (port->tx_fc)
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mvpp2_rxq_disable_fc(port);
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}
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/* Init all Rx queues for port */
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@ -3025,6 +3132,10 @@ static int mvpp2_setup_rxqs(struct mvpp2_port *port)
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if (err)
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goto err_cleanup;
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}
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if (port->tx_fc)
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mvpp2_rxq_enable_fc(port);
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return 0;
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err_cleanup:
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@ -4324,6 +4435,8 @@ static int mvpp2_check_ringparam_valid(struct net_device *dev,
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if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
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new_rx_pending = MVPP2_MAX_RXD_MAX;
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else if (ring->rx_pending < MSS_THRESHOLD_START)
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new_rx_pending = MSS_THRESHOLD_START;
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else if (!IS_ALIGNED(ring->rx_pending, 16))
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new_rx_pending = ALIGN(ring->rx_pending, 16);
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@ -7156,6 +7269,9 @@ static int mvpp2_probe(struct platform_device *pdev)
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priv->hw_version = MVPP23;
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}
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/* Init mss lock */
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spin_lock_init(&priv->mss_spinlock);
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/* Initialize network controller */
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err = mvpp2_init(pdev, priv);
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if (err < 0) {
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