[IA64] Optional method to purge the TLB on SN systems
This patch adds an optional method for purging the TLB on SN IA64 systems. The change should not affect any non-SN system. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>hifive-unleashed-5.1
Jack Steiner
Tony Luck
parent
8737d59579
commit
3be44b9cc3
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@ -39,6 +39,7 @@
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#include <asm/machvec.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_PERFMON
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# include <asm/perfmon.h>
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@ -127,8 +128,10 @@ void destroy_irq(unsigned int irq)
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#ifdef CONFIG_SMP
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# define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
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# define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
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#else
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# define IS_RESCHEDULE(vec) (0)
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# define IS_LOCAL_TLB_FLUSH(vec) (0)
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#endif
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/*
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* That's where the IVT branches when we get an external
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@ -180,8 +183,11 @@ ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
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saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
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ia64_srlz_d();
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while (vector != IA64_SPURIOUS_INT_VECTOR) {
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if (unlikely(IS_RESCHEDULE(vector)))
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kstat_this_cpu.irqs[vector]++;
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if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
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smp_local_flush_tlb();
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kstat_this_cpu.irqs[vector]++;
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} else if (unlikely(IS_RESCHEDULE(vector)))
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kstat_this_cpu.irqs[vector]++;
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else {
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ia64_setreg(_IA64_REG_CR_TPR, vector);
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ia64_srlz_d();
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@ -227,8 +233,11 @@ void ia64_process_pending_intr(void)
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* Perform normal interrupt style processing
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*/
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while (vector != IA64_SPURIOUS_INT_VECTOR) {
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if (unlikely(IS_RESCHEDULE(vector)))
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kstat_this_cpu.irqs[vector]++;
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if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
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smp_local_flush_tlb();
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kstat_this_cpu.irqs[vector]++;
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} else if (unlikely(IS_RESCHEDULE(vector)))
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kstat_this_cpu.irqs[vector]++;
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else {
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struct pt_regs *old_regs = set_irq_regs(NULL);
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@ -260,12 +269,12 @@ void ia64_process_pending_intr(void)
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#ifdef CONFIG_SMP
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extern irqreturn_t handle_IPI (int irq, void *dev_id);
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static irqreturn_t dummy_handler (int irq, void *dev_id)
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{
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BUG();
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}
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extern irqreturn_t handle_IPI (int irq, void *dev_id);
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static struct irqaction ipi_irqaction = {
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.handler = handle_IPI,
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@ -278,6 +287,13 @@ static struct irqaction resched_irqaction = {
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.flags = IRQF_DISABLED,
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.name = "resched"
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};
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static struct irqaction tlb_irqaction = {
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.handler = dummy_handler,
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.flags = SA_INTERRUPT,
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.name = "tlb_flush"
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};
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#endif
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void
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@ -303,6 +319,7 @@ init_IRQ (void)
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#ifdef CONFIG_SMP
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register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
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register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
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register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
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#endif
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#ifdef CONFIG_PERFMON
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pfm_init_percpu();
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@ -49,6 +49,18 @@
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#include <asm/unistd.h>
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#include <asm/mca.h>
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/*
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* Note: alignment of 4 entries/cacheline was empirically determined
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* to be a good tradeoff between hot cachelines & spreading the array
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* across too many cacheline.
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*/
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static struct local_tlb_flush_counts {
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unsigned int count;
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} __attribute__((__aligned__(32))) local_tlb_flush_counts[NR_CPUS];
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static DEFINE_PER_CPU(unsigned int, shadow_flush_counts[NR_CPUS]) ____cacheline_aligned;
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/*
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* Structure and data for smp_call_function(). This is designed to minimise static memory
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* requirements. It also looks cleaner.
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@ -248,6 +260,62 @@ smp_send_reschedule (int cpu)
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platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0);
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}
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/*
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* Called with preeemption disabled.
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*/
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static void
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smp_send_local_flush_tlb (int cpu)
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{
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platform_send_ipi(cpu, IA64_IPI_LOCAL_TLB_FLUSH, IA64_IPI_DM_INT, 0);
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}
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void
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smp_local_flush_tlb(void)
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{
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/*
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* Use atomic ops. Otherwise, the load/increment/store sequence from
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* a "++" operation can have the line stolen between the load & store.
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* The overhead of the atomic op in negligible in this case & offers
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* significant benefit for the brief periods where lots of cpus
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* are simultaneously flushing TLBs.
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*/
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ia64_fetchadd(1, &local_tlb_flush_counts[smp_processor_id()].count, acq);
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local_flush_tlb_all();
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}
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#define FLUSH_DELAY 5 /* Usec backoff to eliminate excessive cacheline bouncing */
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void
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smp_flush_tlb_cpumask(cpumask_t xcpumask)
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{
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unsigned int *counts = __ia64_per_cpu_var(shadow_flush_counts);
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cpumask_t cpumask = xcpumask;
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int mycpu, cpu, flush_mycpu = 0;
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preempt_disable();
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mycpu = smp_processor_id();
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for_each_cpu_mask(cpu, cpumask)
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counts[cpu] = local_tlb_flush_counts[cpu].count;
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mb();
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for_each_cpu_mask(cpu, cpumask) {
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if (cpu == mycpu)
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flush_mycpu = 1;
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else
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smp_send_local_flush_tlb(cpu);
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}
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if (flush_mycpu)
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smp_local_flush_tlb();
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for_each_cpu_mask(cpu, cpumask)
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while(counts[cpu] == local_tlb_flush_counts[cpu].count)
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udelay(FLUSH_DELAY);
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preempt_enable();
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}
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void
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smp_flush_tlb_all (void)
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{
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@ -46,6 +46,9 @@ DECLARE_PER_CPU(struct ptc_stats, ptcstats);
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static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
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/* 0 = old algorithm (no IPI flushes), 1 = ipi deadlock flush, 2 = ipi instead of SHUB ptc, >2 = always ipi */
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static int sn2_flush_opt = 0;
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extern unsigned long
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sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
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volatile unsigned long *, unsigned long,
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@ -76,6 +79,8 @@ struct ptc_stats {
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unsigned long shub_itc_clocks;
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unsigned long shub_itc_clocks_max;
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unsigned long shub_ptc_flushes_not_my_mm;
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unsigned long shub_ipi_flushes;
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unsigned long shub_ipi_flushes_itc_clocks;
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};
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#define sn2_ptctest 0
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@ -121,6 +126,18 @@ void sn_tlb_migrate_finish(struct mm_struct *mm)
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flush_tlb_mm(mm);
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}
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static void
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sn2_ipi_flush_all_tlb(struct mm_struct *mm)
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{
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unsigned long itc;
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itc = ia64_get_itc();
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smp_flush_tlb_cpumask(mm->cpu_vm_mask);
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itc = ia64_get_itc() - itc;
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__get_cpu_var(ptcstats).shub_ipi_flushes_itc_clocks += itc;
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__get_cpu_var(ptcstats).shub_ipi_flushes++;
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}
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/**
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* sn2_global_tlb_purge - globally purge translation cache of virtual address range
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* @mm: mm_struct containing virtual address range
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@ -154,7 +171,12 @@ sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
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unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
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short nasids[MAX_NUMNODES], nix;
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nodemask_t nodes_flushed;
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int active, max_active, deadlock;
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int active, max_active, deadlock, flush_opt = sn2_flush_opt;
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if (flush_opt > 2) {
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sn2_ipi_flush_all_tlb(mm);
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return;
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}
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nodes_clear(nodes_flushed);
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i = 0;
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@ -189,6 +211,12 @@ sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
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return;
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}
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if (flush_opt == 2) {
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sn2_ipi_flush_all_tlb(mm);
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preempt_enable();
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return;
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}
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itc = ia64_get_itc();
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nix = 0;
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for_each_node_mask(cnode, nodes_flushed)
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@ -256,6 +284,8 @@ sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
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}
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if (active >= max_active || i == (nix - 1)) {
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if ((deadlock = wait_piowc())) {
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if (flush_opt == 1)
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goto done;
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sn2_ptc_deadlock_recovery(nasids, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
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if (reset_max_active_on_deadlock())
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max_active = 1;
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@ -267,6 +297,7 @@ sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
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start += (1UL << nbits);
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} while (start < end);
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done:
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itc2 = ia64_get_itc() - itc2;
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__get_cpu_var(ptcstats).shub_itc_clocks += itc2;
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if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
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@ -279,6 +310,11 @@ sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
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spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
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if (flush_opt == 1 && deadlock) {
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__get_cpu_var(ptcstats).deadlocks++;
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sn2_ipi_flush_all_tlb(mm);
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}
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preempt_enable();
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}
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@ -425,24 +461,42 @@ static int sn2_ptc_seq_show(struct seq_file *file, void *data)
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if (!cpu) {
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seq_printf(file,
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"# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2\n");
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seq_printf(file, "# ptctest %d\n", sn2_ptctest);
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"# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2 ipi_fluches ipi_nsec\n");
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seq_printf(file, "# ptctest %d, flushopt %d\n", sn2_ptctest, sn2_flush_opt);
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}
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if (cpu < NR_CPUS && cpu_online(cpu)) {
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stat = &per_cpu(ptcstats, cpu);
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seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
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seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
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stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
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stat->deadlocks,
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1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
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1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
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1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec,
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stat->shub_ptc_flushes_not_my_mm,
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stat->deadlocks2);
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stat->deadlocks2,
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stat->shub_ipi_flushes,
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1000 * stat->shub_ipi_flushes_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec);
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}
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return 0;
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}
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static ssize_t sn2_ptc_proc_write(struct file *file, const char __user *user, size_t count, loff_t *data)
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{
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int cpu;
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char optstr[64];
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if (copy_from_user(optstr, user, count))
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return -EFAULT;
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optstr[count - 1] = '\0';
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sn2_flush_opt = simple_strtoul(optstr, NULL, 0);
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for_each_online_cpu(cpu)
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memset(&per_cpu(ptcstats, cpu), 0, sizeof(struct ptc_stats));
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return count;
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}
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static struct seq_operations sn2_ptc_seq_ops = {
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.start = sn2_ptc_seq_start,
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.next = sn2_ptc_seq_next,
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@ -458,6 +512,7 @@ static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
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static const struct file_operations proc_sn2_ptc_operations = {
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.open = sn2_ptc_proc_open,
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.read = seq_read,
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.write = sn2_ptc_proc_write,
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.llseek = seq_lseek,
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.release = seq_release,
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};
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@ -66,6 +66,7 @@ extern int ia64_last_device_vector;
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#define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */
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#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */
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#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
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#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */
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#define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */
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#define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */
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@ -27,9 +27,11 @@ extern void local_flush_tlb_all (void);
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#ifdef CONFIG_SMP
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extern void smp_flush_tlb_all (void);
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extern void smp_flush_tlb_mm (struct mm_struct *mm);
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extern void smp_flush_tlb_cpumask (cpumask_t xcpumask);
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# define flush_tlb_all() smp_flush_tlb_all()
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#else
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# define flush_tlb_all() local_flush_tlb_all()
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# define smp_flush_tlb_cpumask(m) local_flush_tlb_all()
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#endif
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static inline void
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@ -94,6 +96,15 @@ flush_tlb_pgtables (struct mm_struct *mm, unsigned long start, unsigned long end
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*/
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}
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/*
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* Flush the local TLB. Invoked from another cpu using an IPI.
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*/
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#ifdef CONFIG_SMP
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void smp_local_flush_tlb(void);
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#else
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#define smp_local_flush_tlb()
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#endif
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#define flush_tlb_kernel_range(start, end) flush_tlb_all() /* XXX fix me */
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#endif /* _ASM_IA64_TLBFLUSH_H */
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