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clk: meson: gxbb: add cts_mclk_i958 

Add the spdif master clock also referred as cts_mclk_i958

Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
hifive-unleashed-5.1
Jerome Brunet 2017-02-20 18:02:34 +01:00
parent 4087bd4b21
commit 3c277c247e
2 changed files with 56 additions and 1 deletions
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52
drivers/clk/meson/gxbb.c
View File

@ -890,6 +890,49 @@ static struct clk_gate gxbb_cts_amclk = {
},
};
static struct clk_mux gxbb_cts_mclk_i958_sel = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.mask = 0x3,
.shift = 25,
/* Default parent unknown (register reset value: 0) */
.table = (u32[]){ 1, 2, 3 },
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958_sel",
.ops = &clk_mux_ops,
.parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
.num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_divider gxbb_cts_mclk_i958_div = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.shift = 16,
.width = 8,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
},
};
static struct clk_gate gxbb_cts_mclk_i958 = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.bit_idx = 24,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "cts_mclk_i958_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@ -1093,6 +1136,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
},
.num = NR_CLKS,
};
@ -1209,6 +1255,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
},
.num = NR_CLKS,
};
@ -1322,6 +1371,7 @@ static struct clk_gate *const gxbb_clk_gates[] = {
&gxbb_mali_0,
&gxbb_mali_1,
&gxbb_cts_amclk,
&gxbb_cts_mclk_i958,
};
static struct clk_mux *const gxbb_clk_muxes[] = {
@ -1331,6 +1381,7 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
&gxbb_mali_1_sel,
&gxbb_mali,
&gxbb_cts_amclk_sel,
&gxbb_cts_mclk_i958_sel,
};
static struct clk_divider *const gxbb_clk_dividers[] = {
@ -1338,6 +1389,7 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
&gxbb_sar_adc_clk_div,
&gxbb_mali_0_div,
&gxbb_mali_1_div,
&gxbb_cts_mclk_i958_div,
};
static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {

5
drivers/clk/meson/gxbb.h
View File

@ -280,8 +280,11 @@
#define CLKID_CTS_AMCLK 107
#define CLKID_CTS_AMCLK_SEL 108
#define CLKID_CTS_AMCLK_DIV 109
#define CLKID_CTS_MCLK_I958 110
#define CLKID_CTS_MCLK_I958_SEL 111
#define CLKID_CTS_MCLK_I958_DIV 112
#define NR_CLKS 110
#define NR_CLKS 113
/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>