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This is the bulk of pin control changes for the v5.4 kernel 

cycle:
 
 Core changes:
 
 - Fix errors in example code in the documentation.
 
 New drivers:
 
 - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to
   the Ingenic driver.
 
 - Support Cirrus Logic Madera CS47L92 and CS47L15.
 
 - Support Allwinner Sunxi V3S.
 
 - Support Aspeed 2600 BMC.
 
 - Support Qualcomm SC7180.
 
 - Support Marvell MVEBU CS115.
 
 Driver improvements:
 
 - Clean up a few drivers to use the devm_platform_ioremap_resource()
   helper.
 
 - Pass the irqchip when registering the gpio_chip in some pin
   controllers that are also GPIO controllers.
 
 - Support suspend/resume in the Tegra driver.
 
 - Support pull-up on the Broadcom BCM2711.
 
 - The Intel driver can now request locked pads.
 
 - Fix the UFS reset pin in the Qualcomm SDM845 driver.
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Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...
alistair/sunxi64-5.4-dsi
Linus Torvalds 2019-09-19 14:19:33 -07:00
parent 32b90daf5c cb0438e443
commit 3c2edc36a7
96 changed files with 7984 additions and 2373 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
View File

@ -78,8 +78,8 @@ Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
Required properties:
- compatible: "marvell,armada-7k-pinctrl",
"marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl"
- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl",
"marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl"
depending on the specific variant of the SoC being used.
Available mpp pins/groups and functions:

2
Documentation/devicetree/bindings/mfd/aspeed-scu.txt
View File

@ -4,9 +4,7 @@ configuring elements such as clocks, pinmux, and reset.
Required properties:
- compatible: One of:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
"aspeed,g4-scu", "syscon", "simple-mfd"
"aspeed,ast2500-scu", "syscon", "simple-mfd"
"aspeed,g5-scu", "syscon", "simple-mfd"
- reg: contains the offset and length of the SCU memory region
- #clock-cells: should be set to <1> - the system controller is also a

2
Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
View File

@ -26,9 +26,7 @@ property:
- compatible : Should be one of the following:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
"aspeed,g4-scu", "syscon", "simple-mfd"
"aspeed,ast2500-scu", "syscon", "simple-mfd"
"aspeed,g5-scu", "syscon", "simple-mfd"
Example
===================

45
Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View File

@ -15,16 +15,13 @@ description: |+
- compatible: Should be one of the following:
"aspeed,ast2400-scu", "syscon", "simple-mfd"
"aspeed,g4-scu", "syscon", "simple-mfd"
Refer to the the bindings described in
Documentation/devicetree/bindings/mfd/syscon.txt
properties:
compatible:
enum:
- aspeed,ast2400-pinctrl
- aspeed,g4-pinctrl
const: aspeed,ast2400-pinctrl
patternProperties:
'^.*$':
@ -35,28 +32,24 @@ patternProperties:
"^function|groups$":
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13",
"ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7",
"ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "EXTRST", "FLACK",
"FLBUSY", "FLWP", "GPID", "GPID0", "GPID2", "GPID4", "GPID6",
"GPIE0", "GPIE2", "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12",
"I2C13", "I2C14", "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8",
"I2C9", "LPCPD", "LPCPME", "LPCRST", "LPCSMI", "MAC1LINK",
"MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4",
"NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3",
"NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NDTS4", "NRI1",
"NRI2", "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "OSCCLK",
"PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7",
"RGMII1", "RGMII2", "RMII1", "RMII2", "ROM16", "ROM8", "ROMCS1",
"ROMCS2", "ROMCS3", "ROMCS4", "RXD1", "RXD2", "RXD3", "RXD4",
"SALT1", "SALT2", "SALT3", "SALT4", "SD1", "SD2", "SGPMCK",
"SGPMI", "SGPMLD", "SGPMO", "SGPSCK", "SGPSI0", "SGPSI1", "SGPSLD",
"SIOONCTRL", "SIOPBI", "SIOPBO", "SIOPWREQ", "SIOPWRGD", "SIOS3",
"SIOS5", "SIOSCI", "SPI1", "SPI1DEBUG", "SPI1PASSTHRU", "SPICS1",
"TIMER3", "TIMER4", "TIMER5", "TIMER6", "TIMER7", "TIMER8", "TXD1",
"TXD2", "TXD3", "TXD4", "UART6", "USB11D1", "USB11H2", "USB2D1",
"USB2H1", "USBCKI", "VGABIOS_ROM", "VGAHS", "VGAVS", "VPI18",
"VPI24", "VPI30", "VPO12", "VPO24", "WDTRST1", "WDTRST2" ]
- enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14,
ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT,
DDCCLK, DDCDAT, EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2,
GPID4, GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12,
I2C13, I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD,
LPCPME, LPCRST, LPCSMI, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1,
NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NDTS4, NRI1, NRI2,
NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, PWM1, PWM2, PWM3,
PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, ROM16,
ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, RXD4,
SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG,
SPI1PASSTHRU, SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7,
TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1,
USB2H1, USBCKI, VGABIOS_ROM, VGAHS, VGAVS, VPI18, VPI24, VPI30,
VPO12, VPO24, WDTRST1, WDTRST2 ]
required:
- compatible

49
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View File

@ -22,9 +22,7 @@ description: |+
properties:
compatible:
enum:
- aspeed,ast2500-pinctrl
- aspeed,g5-pinctrl
const: aspeed,ast2500-pinctrl
aspeed,external-nodes:
minItems: 2
maxItems: 2
@ -44,31 +42,26 @@ patternProperties:
"^function|groups$":
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13",
"ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7",
"ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "ESPI", "FWSPICS1",
"FWSPICS2", "GPID0", "GPID2", "GPID4", "GPID6", "GPIE0", "GPIE2",
"GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12", "I2C13", "I2C14",
"I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8", "I2C9", "LAD0",
"LAD1", "LAD2", "LAD3", "LCLK", "LFRAME", "LPCHC", "LPCPD",
"LPCPLUS", "LPCPME", "LPCRST", "LPCSMI", "LSIRQ", "MAC1LINK",
"MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4",
"NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3",
"NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NRI1", "NRI2",
"NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "NRTS4", "OSCCLK",
"PEWAKE", "PNOR", "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5",
"PWM6", "PWM7", "RGMII1", "RGMII2", "RMII1", "RMII2", "RXD1",
"RXD2", "RXD3", "RXD4", "SALT1", "SALT10", "SALT11", "SALT12",
"SALT13", "SALT14", "SALT2", "SALT3", "SALT4", "SALT5", "SALT6",
"SALT7", "SALT8", "SALT9", "SCL1", "SCL2", "SD1", "SD2", "SDA1",
"SDA2", "SGPS1", "SGPS2", "SIOONCTRL", "SIOPBI", "SIOPBO",
"SIOPWREQ", "SIOPWRGD", "SIOS3", "SIOS5", "SIOSCI", "SPI1",
"SPI1CS1", "SPI1DEBUG", "SPI1PASSTHRU", "SPI2CK", "SPI2CS0",
"SPI2CS1", "SPI2MISO", "SPI2MOSI", "TIMER3", "TIMER4", "TIMER5",
"TIMER6", "TIMER7", "TIMER8", "TXD1", "TXD2", "TXD3", "TXD4",
"UART6", "USB11BHID", "USB2AD", "USB2AH", "USB2BD", "USB2BH",
"USBCKI", "VGABIOSROM", "VGAHS", "VGAVS", "VPI24", "VPO",
"WDTRST1", "WDTRST2", ]
- enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14,
ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT,
DDCCLK, DDCDAT, ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4,
GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13,
I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LAD0, LAD1,
LAD2, LAD3, LCLK, LFRAME, LPCHC, LPCPD, LPCPLUS, LPCPME, LPCRST,
LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2,
NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, PWM1, PWM2,
PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, RXD1,
RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI,
SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1,
SPI1DEBUG, SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO,
SPI2MOSI, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1,
TXD2, TXD3, TXD4, UART6, USB11BHID, USB2AD, USB2AH, USB2BD,
USB2BH, USBCKI, VGABIOSROM, VGAHS, VGAVS, VPI24, VPO, WDTRST1,
WDTRST2, ]
required:
- compatible

115
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml 100644
View File

@ -0,0 +1,115 @@
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2600-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED AST2600 Pin Controller
maintainers:
- Andrew Jeffery <andrew@aj.id.au>
description: |+
The pin controller node should be the child of a syscon node with the
required property:
- compatible: Should be one of the following:
"aspeed,ast2600-scu", "syscon", "simple-mfd"
Refer to the the bindings described in
Documentation/devicetree/bindings/mfd/syscon.txt
properties:
compatible:
const: aspeed,ast2600-pinctrl
patternProperties:
'^.*$':
if:
type: object
then:
properties:
function:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1,
GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2,
GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12,
I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7,
I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC,
LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7,
PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5,
SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO,
SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1,
SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5,
TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1,
TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7,
UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
WDTRST4, ]
groups:
allOf:
- $ref: "/schemas/types.yaml#/definitions/string"
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0,
GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1,
I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3,
I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6,
JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3,
MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1,
NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE,
PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1,
PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3,
PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1,
SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1,
SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1,
SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0,
SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7,
SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD,
SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13,
TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8,
TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4,
UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
WDTRST4, ]
required:
- compatible
examples:
- |
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0xf6c>;
pinctrl: pinctrl {
compatible = "aspeed,g6-pinctrl";
pinctrl_pwm10g1_default: pwm10g1_default {
function = "PWM10";
groups = "PWM10G1";
};
pinctrl_gpioh0_unbiased_default: gpioh0 {
pins = "A18";
bias-disable;
};
};
};

1
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
View File

@ -8,6 +8,7 @@ Required properties:
- compatible: should be one of:
"brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
"brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
"brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
- reg: Should contain the physical address of the GPIO module's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the

17
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
View File

@ -1,18 +1,18 @@
Ingenic jz47xx pin controller
Ingenic XBurst pin controller
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
be used as GPIOs, multiplexed device functions are configured within the
GPIO port configuration registers and it is typical to refer to pins using the
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
total of 192 pins.
PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO
ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780
contains 6 GPIO ports, PA to PF, for a total of 192 pins.
Required properties:
@ -21,8 +21,13 @@ Required properties:
- compatible: One of:
- "ingenic,jz4740-pinctrl"
- "ingenic,jz4725b-pinctrl"
- "ingenic,jz4760-pinctrl"
- "ingenic,jz4760b-pinctrl"
- "ingenic,jz4770-pinctrl"
- "ingenic,jz4780-pinctrl"
- "ingenic,x1000-pinctrl"
- "ingenic,x1000e-pinctrl"
- "ingenic,x1500-pinctrl"
- reg: Address range of the pinctrl registers.
@ -31,8 +36,10 @@ Required properties for sub-nodes (GPIO chips):
- compatible: Must contain one of:
- "ingenic,jz4740-gpio"
- "ingenic,jz4760-gpio"
- "ingenic,jz4770-gpio"
- "ingenic,jz4780-gpio"
- "ingenic,x1000-gpio"
- reg: The GPIO bank number.
- interrupt-controller: Marks the device node as an interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.

5
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
View File

@ -132,9 +132,8 @@ to specify in a pin configuration subnode:
qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
tsense_pwm1, tsense_pwm2, tsif0, tsif1,
uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,

6
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View File

@ -21,6 +21,8 @@ PMIC's from Qualcomm.
"qcom,pmi8994-gpio"
"qcom,pmi8998-gpio"
"qcom,pms405-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@ -94,6 +96,10 @@ to specify in a pin configuration subnode:
gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994
gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7
and gpio8)
gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
gpio1-gpio12 for pm8150l (hole on gpio7)
- function:
Usage: required

186
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt 100644
View File

@ -0,0 +1,186 @@
Qualcomm Technologies, Inc. SC7180 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
SC7180 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,sc7180-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the north, south and west
TLMM tiles
- reg-names:
Usage: required
Value type: <prop-encoded-array>
Definition: names for the cells of reg, must contain "north", "south"
and "west".
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Value type: <prop-encoded-array>
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Value type: <prop-encoded-array>
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio118
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
ufs_reset
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
atest_char1, atest_char2, atest_char3, atest_tsens,
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
atest_usb21, atest_usb22, atest_usb23, audio_ref,
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2,
gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0,
mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
qspi_data, qup00, qup01, qup02, qup03, qup04, qup05,
qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb,
sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
wlan2_adc1,
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configured as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@3500000 {
compatible = "qcom,sc7180-pinctrl";
reg = <0x3500000 0x300000>,
<0x3900000 0x300000>,
<0x3D00000 0x300000>;
reg-names = "west", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 119>;
gpio-reserved-ranges = <0 4>, <106 4>;
interrupt-controller;
#interrupt-cells = <2>;
};

6
Documentation/driver-api/pinctl.rst
View File

@ -638,8 +638,8 @@ group of pins would work something like this::
}
static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
unsigned ** const pins,
unsigned * const num_pins)
const unsigned ** pins,
unsigned * num_pins)
{
*pins = (unsigned *) foo_groups[selector].pins;
*num_pins = foo_groups[selector].num_pins;
@ -705,7 +705,7 @@ group of pins would work something like this::
{
u8 regbit = (1 << selector + group);
writeb((readb(MUX)|regbit), MUX)
writeb((readb(MUX)|regbit), MUX);
return 0;
}

3
drivers/gpio/gpiolib.c
View File

@ -1084,7 +1084,8 @@ static long gpio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
test_bit(FLAG_IS_HOGGED, &desc->flags) ||
test_bit(FLAG_USED_AS_IRQ, &desc->flags) ||
test_bit(FLAG_EXPORT, &desc->flags) ||
test_bit(FLAG_SYSFS, &desc->flags))
test_bit(FLAG_SYSFS, &desc->flags) ||
!pinctrl_gpio_can_use_line(chip->base + lineinfo.line_offset))
lineinfo.flags |= GPIOLINE_FLAG_KERNEL;
if (test_bit(FLAG_IS_OUT, &desc->flags))
lineinfo.flags |= GPIOLINE_FLAG_IS_OUT;

8
drivers/pinctrl/aspeed/Kconfig
View File

@ -23,3 +23,11 @@ config PINCTRL_ASPEED_G5
help
Say Y here to enable pin controller support for Aspeed's 5th
generation SoCs. GPIO is provided by a separate GPIO driver.
config PINCTRL_ASPEED_G6
bool "Aspeed G6 SoC pin control"
depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF
select PINCTRL_ASPEED
help
Say Y here to enable pin controller support for Aspeed's 6th
generation SoCs. GPIO is provided by a separate GPIO driver.

1
drivers/pinctrl/aspeed/Makefile
View File

@ -5,3 +5,4 @@ ccflags-y += $(call cc-option,-Woverride-init)
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o
obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o

1825
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
View File

File diff suppressed because it is too large Load Diff

1869
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
View File

File diff suppressed because it is too large Load Diff

2395
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c 100644
View File

File diff suppressed because it is too large Load Diff

241
drivers/pinctrl/aspeed/pinmux-aspeed.h
View File

@ -162,10 +162,11 @@
* * Enabling lower priority signals requires higher priority signals be
* disabled
*
* * A function represents a set of signals; functions are distinct if their
* sets of signals are not equal
* * A function represents a set of signals; functions are distinct if they
* do not share a subset of signals (and may be distinct if they are a
* strict subset).
*
* * Signals participate in one or more functions
* * Signals participate in one or more functions or groups
*
* * A function is described by an expression of one or more signal
* descriptors, which compare bit values in a register
@ -507,20 +508,21 @@ struct aspeed_pin_desc {
* @idx: The bit index in the register
*/
#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0)
#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
#define SIG_DESC_LIST_DECL(sig, func, ...) \
static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
#define SIG_DESC_LIST_DECL(sig, group, ...) \
static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \
{ __VA_ARGS__ }
#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
#define SIG_EXPR_DECL_(sig, func) \
static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
#define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group
#define SIG_EXPR_DECL_(sig, group, func) \
static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \
{ \
.signal = #sig, \
.function = #func, \
.ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
.descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
.ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \
.descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \
}
/**
@ -533,16 +535,16 @@ struct aspeed_pin_desc {
*
* For example, the following declares the ROMD8 signal for the ROM16 function:
*
* SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
* SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
*
* And with multiple signal descriptors:
*
* SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* { HW_STRAP1, GENMASK(1, 0), 0, 0 });
*/
#define SIG_EXPR_DECL(sig, func, ...) \
SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, func)
#define SIG_EXPR_DECL(sig, group, func, ...) \
SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, group, func)
/**
* Declare a pointer to a signal expression
@ -550,9 +552,9 @@ struct aspeed_pin_desc {
* @sig: The macro symbol name for the signal (subjected to token pasting)
* @func: The macro symbol name for the function (subjected to token pasting)
*/
#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
#define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group))
#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
#define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group
/**
* Declare a signal expression list for reference in a struct aspeed_pin_prio.
@ -563,49 +565,138 @@ struct aspeed_pin_desc {
* For example, the 16-bit ROM bus can be enabled by one of two possible signal
* expressions:
*
* SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
* SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
* SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* { HW_STRAP1, GENMASK(1, 0), 0, 0 });
* SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
* SIG_EXPR_PTR(ROMD8, ROM16S));
*/
#define SIG_EXPR_LIST_DECL(sig, ...) \
static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
#define SIG_EXPR_LIST_DECL(sig, group, ...) \
static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\
{ __VA_ARGS__, NULL }
#define stringify(x) #x
#define istringify(x) stringify(x)
/**
* Create an expression symbol alias from (signal, group) to (pin, signal).
*
* @pin: The pin number
* @sig: The signal name
* @group: The name of the group of which the pin is a member that is
* associated with the function's signal
*
* Using an alias in this way enables detection of copy/paste errors (defining
* the signal for a group multiple times) whilst enabling multiple pin groups
* to exist for a signal without intrusive side-effects on defining the list of
* signals available on a pin.
*/
#define SIG_EXPR_LIST_ALIAS(pin, sig, group) \
static const struct aspeed_sig_expr *\
SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
__attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group)))))
/**
* A short-hand macro for declaring a function expression and an expression
* list with a single function.
* list with a single expression (SE) and a single group (SG) of pins.
*
* @func: A macro symbol name for the function (is subjected to token pasting)
* @pin: The pin the signal will be routed to
* @sig: The signal that will be routed to the pin for the function
* @func: A macro symbol name for the function
* @...: Function descriptors that define the function expression
*
* For example, signal NCTS6 participates in its own function with one group:
*
* SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
* SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
*/
#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
#define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \
SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, func); \
SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
SIG_EXPR_DECL_(sig, func, func); \
SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \
SIG_EXPR_LIST_ALIAS(pin, sig, func)
#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
/**
* Similar to the above, but for pins with a single expression (SE) and
* multiple groups (MG) of pins.
*
* @pin: The pin the signal will be routed to
* @sig: The signal that will be routed to the pin for the function
* @group: The name of the function's pin group in which the pin participates
* @func: A macro symbol name for the function
* @...: Function descriptors that define the function expression
*/
#define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \
SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, group, func); \
SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \
SIG_EXPR_LIST_ALIAS(pin, sig, group)
#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
/**
* Similar to the above, but for pins with a dual expressions (DE) and
* and a single group (SG) of pins.
*
* @pin: The pin the signal will be routed to
* @sig: The signal that will be routed to the pin for the function
* @group: The name of the function's pin group in which the pin participates
* @func: A macro symbol name for the function
* @...: Function descriptors that define the function expression
*/
#define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \
SIG_EXPR_LIST_DECL(sig, f0, \
SIG_EXPR_PTR(sig, f0), \
SIG_EXPR_PTR(sig, f1)); \
SIG_EXPR_LIST_ALIAS(pin, sig, f0)
#define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group)
#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
#define PIN_SYM(pin) pin_ ## pin
#define MS_PIN_DECL_(pin, ...) \
#define PIN_DECL_(pin, ...) \
static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
{ __VA_ARGS__, NULL }; \
static const struct aspeed_pin_desc PIN_SYM(pin) = \
{ #pin, PIN_EXPRS_PTR(pin) }
/**
* Declare a multi-signal pin
* Declare a single signal pin
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @sig: Macro name for the signal (subjected to stringification)
*
* For example:
*
* #define E3 80
* SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
* PIN_DECL_1(E3, GPIOK0, SCL5);
*/
#define PIN_DECL_1(pin, other, sig) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
SIG_EXPR_LIST_PTR(pin, other))
/**
* Single signal, single function pin declaration
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @sig: Macro name for the signal (subjected to stringification)
* @...: Signal descriptors that define the function expression
*
* For example:
*
* SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
*/
#define SSSF_PIN_DECL(pin, other, sig, ...) \
SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
SIG_EXPR_LIST_PTR(pin, other)); \
FUNC_GROUP_DECL(sig, pin)
/**
* Declare a two-signal pin
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
@ -621,59 +712,41 @@ struct aspeed_pin_desc {
* SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
* SIG_EXPR_PTR(ROMD8, ROM16S));
* SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
* MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
* PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
*/
#define MS_PIN_DECL(pin, other, high, low) \
SIG_EXPR_LIST_DECL_SINGLE(other, other); \
MS_PIN_DECL_(pin, \
SIG_EXPR_LIST_PTR(high), \
SIG_EXPR_LIST_PTR(low), \
SIG_EXPR_LIST_PTR(other))
#define PIN_DECL_2(pin, other, high, low) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, \
SIG_EXPR_LIST_PTR(pin, high), \
SIG_EXPR_LIST_PTR(pin, low), \
SIG_EXPR_LIST_PTR(pin, other))
#define PIN_DECL_3(pin, other, high, medium, low) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, \
SIG_EXPR_LIST_PTR(pin, high), \
SIG_EXPR_LIST_PTR(pin, medium), \
SIG_EXPR_LIST_PTR(pin, low), \
SIG_EXPR_LIST_PTR(pin, other))
#define GROUP_SYM(group) group_pins_ ## group
#define GROUP_DECL(group, ...) \
static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
#define FUNC_SYM(func) func_groups_ ## func
#define FUNC_DECL_(func, ...) \
static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
#define PIN_GROUP_SYM(func) pins_ ## func
#define FUNC_GROUP_SYM(func) groups_ ## func
#define FUNC_GROUP_DECL(func, ...) \
static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
static const char *FUNC_GROUP_SYM(func)[] = { #func }
GROUP_DECL(func, __VA_ARGS__); \
FUNC_DECL_(func, #func)
/**
* Declare a single signal pin
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @sig: Macro name for the signal (subjected to stringification)
*
* For example:
*
* #define E3 80
* SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
* SS_PIN_DECL(E3, GPIOK0, SCL5);
*/
#define SS_PIN_DECL(pin, other, sig) \
SIG_EXPR_LIST_DECL_SINGLE(other, other); \
MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
/**
* Single signal, single function pin declaration
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @sig: Macro name for the signal (subjected to stringification)
* @...: Signal descriptors that define the function expression
*
* For example:
*
* SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
*/
#define SSSF_PIN_DECL(pin, other, sig, ...) \
SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
SIG_EXPR_LIST_DECL_SINGLE(other, other); \
MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
FUNC_GROUP_DECL(sig, pin)
#define GPIO_PIN_DECL(pin, gpio) \
SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \
PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio))
struct aspeed_pin_group {
const char *name;
@ -683,8 +756,8 @@ struct aspeed_pin_group {
#define ASPEED_PINCTRL_GROUP(name_) { \
.name = #name_, \
.pins = &(PIN_GROUP_SYM(name_))[0], \
.npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
.pins = &(GROUP_SYM(name_))[0], \
.npins = ARRAY_SIZE(GROUP_SYM(name_)), \
}
struct aspeed_pin_function {
@ -695,8 +768,8 @@ struct aspeed_pin_function {
#define ASPEED_PINCTRL_FUNC(name_, ...) { \
.name = #name_, \
.groups = &FUNC_GROUP_SYM(name_)[0], \
.ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
.groups = &FUNC_SYM(name_)[0], \
.ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \
}
struct aspeed_pinmux_data;

156
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -57,19 +57,27 @@
#define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
#define GPPUD 0x94 /* Pin Pull-up/down Enable */
#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
#define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
#define FSEL_SHIFT(p) (((p) % 10) * 3)
#define GPIO_REG_OFFSET(p) ((p) / 32)
#define GPIO_REG_SHIFT(p) ((p) % 32)
#define PUD_2711_MASK 0x3
#define PUD_2711_REG_OFFSET(p) ((p) / 16)
#define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
/* argument: bcm2835_pinconf_pull */
#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
#define BCM2711_PULL_NONE 0x0
#define BCM2711_PULL_UP 0x1
#define BCM2711_PULL_DOWN 0x2
struct bcm2835_pinctrl {
struct device *dev;
void __iomem *base;
int irq[BCM2835_NUM_IRQS];
/* note: locking assumes each bank will have its own unsigned long */
unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
@ -373,14 +381,14 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
int group;
int i;
for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
if (pc->irq[i] == irq) {
for (i = 0; i < BCM2835_NUM_IRQS; i++) {
if (chip->irq.parents[i] == irq) {
group = i;
break;
}
}
/* This should not happen, every IRQ has a bank */
if (i == ARRAY_SIZE(pc->irq))
if (i == BCM2835_NUM_IRQS)
BUG();
chained_irq_enter(host_chip, desc);
@ -975,6 +983,77 @@ static const struct pinconf_ops bcm2835_pinconf_ops = {
.pin_config_set = bcm2835_pinconf_set,
};
static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
unsigned int pin, unsigned int arg)
{
u32 shifter;
u32 value;
u32 off;
off = PUD_2711_REG_OFFSET(pin);
shifter = PUD_2711_REG_SHIFT(pin);
value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
value &= ~(PUD_2711_MASK << shifter);
value |= (arg << shifter);
bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
}
static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
u32 param, arg;
int i;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
/* convert legacy brcm,pull */
case BCM2835_PINCONF_PARAM_PULL:
if (arg == BCM2835_PUD_UP)
arg = BCM2711_PULL_UP;
else if (arg == BCM2835_PUD_DOWN)
arg = BCM2711_PULL_DOWN;
else
arg = BCM2711_PULL_NONE;
bcm2711_pull_config_set(pc, pin, arg);
break;
/* Set pull generic bindings */
case PIN_CONFIG_BIAS_DISABLE:
bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
break;
case PIN_CONFIG_BIAS_PULL_UP:
bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
break;
/* Set output-high or output-low */
case PIN_CONFIG_OUTPUT:
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
break;
default:
return -ENOTSUPP;
}
} /* for each config */
return 0;
}
static const struct pinconf_ops bcm2711_pinconf_ops = {
.is_generic = true,
.pin_config_get = bcm2835_pinconf_get,
.pin_config_set = bcm2711_pinconf_set,
};
static struct pinctrl_desc bcm2835_pinctrl_desc = {
.name = MODULE_NAME,
.pins = bcm2835_gpio_pins,
@ -990,13 +1069,28 @@ static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
.npins = BCM2835_NUM_GPIOS,
};
static const struct of_device_id bcm2835_pinctrl_match[] = {
{
.compatible = "brcm,bcm2835-gpio",
.data = &bcm2835_pinconf_ops,
},
{
.compatible = "brcm,bcm2711-gpio",
.data = &bcm2711_pinconf_ops,
},
{}
};
static int bcm2835_pinctrl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct bcm2835_pinctrl *pc;
struct gpio_irq_chip *girq;
struct resource iomem;
int err, i;
const struct of_device_id *match;
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
@ -1041,36 +1135,37 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
raw_spin_lock_init(&pc->irq_lock[i]);
}
girq = &pc->gpio_chip.irq;
girq->chip = &bcm2835_gpio_irq_chip;
girq->parent_handler = bcm2835_gpio_irq_handler;
girq->num_parents = BCM2835_NUM_IRQS;
girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
/*
* Use the same handler for all groups: this is necessary
* since we use one gpiochip to cover all lines - the
* irq handler then needs to figure out which group and
* bank that was firing the IRQ and look up the per-group
* and bank data.
*/
for (i = 0; i < BCM2835_NUM_IRQS; i++)
girq->parents[i] = irq_of_parse_and_map(np, i);
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
err = gpiochip_add_data(&pc->gpio_chip, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
return err;
}
err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
0, handle_level_irq, IRQ_TYPE_NONE);
if (err) {
dev_info(dev, "could not add irqchip\n");
return err;
}
for (i = 0; i < BCM2835_NUM_IRQS; i++) {
pc->irq[i] = irq_of_parse_and_map(np, i);
if (pc->irq[i] == 0)
continue;
/*
* Use the same handler for all groups: this is necessary
* since we use one gpiochip to cover all lines - the
* irq handler then needs to figure out which group and
* bank that was firing the IRQ and look up the per-group
* and bank data.
*/
gpiochip_set_chained_irqchip(&pc->gpio_chip,
&bcm2835_gpio_irq_chip,
pc->irq[i],
bcm2835_gpio_irq_handler);
match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
if (match) {
bcm2835_pinctrl_desc.confops =
(const struct pinconf_ops *)match->data;
}
pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
@ -1087,11 +1182,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
return 0;
}
static const struct of_device_id bcm2835_pinctrl_match[] = {
{ .compatible = "brcm,bcm2835-gpio" },
{}
};
static struct platform_driver bcm2835_pinctrl_driver = {
.probe = bcm2835_pinctrl_probe,
.driver = {

1
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
View File

@ -923,7 +923,6 @@ static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
if (!pinctrl->mux_log)
return -ENOMEM;
log = pinctrl->mux_log;
for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG

156
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@ -54,8 +54,12 @@
/* drive strength control for ASIU GPIO */
#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
/* drive strength control for CCM/CRMU (AON) GPIO */
#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00
/* pinconf for CCM GPIO */
#define IPROC_GPIO_PULL_DN_OFFSET 0x10
#define IPROC_GPIO_PULL_UP_OFFSET 0x14
/* pinconf for CRMU(aon) GPIO and CCM GPIO*/
#define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
#define GPIO_BANK_SIZE 0x200
#define NGPIOS_PER_BANK 32
@ -76,6 +80,12 @@ enum iproc_pinconf_param {
IPROC_PINCON_MAX,
};
enum iproc_pinconf_ctrl_type {
IOCTRL_TYPE_AON = 1,
IOCTRL_TYPE_CDRU,
IOCTRL_TYPE_INVALID,
};
/*
* Iproc GPIO core
*
@ -100,9 +110,11 @@ struct iproc_gpio {
void __iomem *base;
void __iomem *io_ctrl;
enum iproc_pinconf_ctrl_type io_ctrl_type;
raw_spinlock_t lock;
struct irq_chip irqchip;
struct gpio_chip gc;
unsigned num_banks;
@ -291,14 +303,6 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
return 0;
}
static struct irq_chip iproc_gpio_irq_chip = {
.name = "bcm-iproc-gpio",
.irq_ack = iproc_gpio_irq_ack,
.irq_mask = iproc_gpio_irq_mask,
.irq_unmask = iproc_gpio_irq_unmask,
.irq_set_type = iproc_gpio_irq_set_type,
};
/*
* Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
*/
@ -355,6 +359,15 @@ static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
return 0;
}
static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
unsigned int shift = IPROC_GPIO_SHIFT(gpio);
return !(readl(chip->base + offset) & BIT(shift));
}
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
@ -461,20 +474,44 @@ static const struct pinctrl_ops iproc_pctrl_ops = {
static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
bool disable, bool pull_up)
{
void __iomem *base;
unsigned long flags;
unsigned int shift;
u32 val_1, val_2;
raw_spin_lock_irqsave(&chip->lock, flags);
if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
base = chip->io_ctrl;
shift = IPROC_GPIO_SHIFT(gpio);
if (disable) {
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false);
val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
if (disable) {
/* no pull-up or pull-down */
val_1 &= ~BIT(shift);
val_2 &= ~BIT(shift);
} else if (pull_up) {
val_1 |= BIT(shift);
val_2 &= ~BIT(shift);
} else {
val_1 &= ~BIT(shift);
val_2 |= BIT(shift);
}
writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
} else {
iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
pull_up);
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true);
if (disable) {
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
false);
} else {
iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
pull_up);
iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
true);
}
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
return 0;
@ -483,14 +520,35 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
bool *disable, bool *pull_up)
{
void __iomem *base;
unsigned long flags;
unsigned int shift;
u32 val_1, val_2;
raw_spin_lock_irqsave(&chip->lock, flags);
*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
base = chip->io_ctrl;
shift = IPROC_GPIO_SHIFT(gpio);
val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
*pull_up = val_1 ? true : false;
*disable = (val_1 | val_2) ? false : true;
} else {
*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
}
#define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
((type) == IOCTRL_TYPE_CDRU) ? \
((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
unsigned strength)
{
@ -505,11 +563,8 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
if (chip->io_ctrl) {
base = chip->io_ctrl;
offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
} else {
base = chip->base;
offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
}
shift = IPROC_GPIO_SHIFT(gpio);
@ -520,11 +575,11 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
raw_spin_lock_irqsave(&chip->lock, flags);
strength = (strength / 2) - 1;
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
val = readl(base + offset);
val &= ~BIT(shift);
val |= ((strength >> i) & 0x1) << shift;
writel(val, base + offset);
offset += 4;
}
raw_spin_unlock_irqrestore(&chip->lock, flags);
@ -541,11 +596,8 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
if (chip->io_ctrl) {
base = chip->io_ctrl;
offset = IPROC_GPIO_DRV0_CTRL_OFFSET;
} else {
base = chip->base;
offset = IPROC_GPIO_REG(gpio,
IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET);
}
shift = IPROC_GPIO_SHIFT(gpio);
@ -553,10 +605,10 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
raw_spin_lock_irqsave(&chip->lock, flags);
*strength = 0;
for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
val = readl(base + offset) & BIT(shift);
val >>= shift;
*strength += (val << i);
offset += 4;
}
/* convert to mA */
@ -734,6 +786,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
u32 ngpios, pinconf_disable_mask = 0;
int irq, ret;
bool no_pinconf = false;
enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
/* NSP does not support drive strength config */
if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
@ -764,8 +817,15 @@ static int iproc_gpio_probe(struct platform_device *pdev)
dev_err(dev, "unable to map I/O memory\n");
return PTR_ERR(chip->io_ctrl);
}
if (of_device_is_compatible(dev->of_node,
"brcm,cygnus-ccm-gpio"))
io_ctrl_type = IOCTRL_TYPE_CDRU;
else
io_ctrl_type = IOCTRL_TYPE_AON;
}
chip->io_ctrl_type = io_ctrl_type;
if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
dev_err(&pdev->dev, "missing ngpios DT property\n");
return -ENODEV;
@ -784,12 +844,42 @@ static int iproc_gpio_probe(struct platform_device *pdev)
gc->free = iproc_gpio_free;
gc->direction_input = iproc_gpio_direction_input;
gc->direction_output = iproc_gpio_direction_output;
gc->get_direction = iproc_gpio_get_direction;
gc->set = iproc_gpio_set;
gc->get = iproc_gpio_get;
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
"gpio-ranges");
/* optional GPIO interrupt support */
irq = platform_get_irq(pdev, 0);
if (irq) {
struct irq_chip *irqc;
struct gpio_irq_chip *girq;
irqc = &chip->irqchip;
irqc->name = "bcm-iproc-gpio";
irqc->irq_ack = iproc_gpio_irq_ack;
irqc->irq_mask = iproc_gpio_irq_mask;
irqc->irq_unmask = iproc_gpio_irq_unmask;
irqc->irq_set_type = iproc_gpio_irq_set_type;
irqc->irq_enable = iproc_gpio_irq_unmask;
irqc->irq_disable = iproc_gpio_irq_mask;
girq = &gc->irq;
girq->chip = irqc;
girq->parent_handler = iproc_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1,
sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->parents[0] = irq;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_simple_irq;
}
ret = gpiochip_add_data(gc, chip);
if (ret < 0) {
dev_err(dev, "unable to add GPIO chip\n");
@ -814,20 +904,6 @@ static int iproc_gpio_probe(struct platform_device *pdev)
}
}
/* optional GPIO interrupt support */
irq = platform_get_irq(pdev, 0);
if (irq) {
ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0,
handle_simple_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(dev, "no GPIO irqchip\n");
goto err_rm_gpiochip;
}
gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq,
iproc_gpio_irq_handler);
}
return 0;
err_rm_gpiochip:

6
drivers/pinctrl/cirrus/Kconfig
View File

@ -15,6 +15,9 @@ config PINCTRL_MADERA
select PINMUX
select GENERIC_PINCONF
config PINCTRL_CS47L15
bool
config PINCTRL_CS47L35
bool
@ -23,3 +26,6 @@ config PINCTRL_CS47L85
config PINCTRL_CS47L90
bool
config PINCTRL_CS47L92
bool

6
drivers/pinctrl/cirrus/Makefile
View File

@ -3,6 +3,9 @@
obj-$(CONFIG_PINCTRL_LOCHNAGAR) += pinctrl-lochnagar.o
pinctrl-madera-objs := pinctrl-madera-core.o
ifeq ($(CONFIG_PINCTRL_CS47L15),y)
pinctrl-madera-objs += pinctrl-cs47l15.o
endif
ifeq ($(CONFIG_PINCTRL_CS47L35),y)
pinctrl-madera-objs += pinctrl-cs47l35.o
endif
@ -12,5 +15,8 @@ endif
ifeq ($(CONFIG_PINCTRL_CS47L90),y)
pinctrl-madera-objs += pinctrl-cs47l90.o
endif
ifeq ($(CONFIG_PINCTRL_CS47L92),y)
pinctrl-madera-objs += pinctrl-cs47l92.o
endif
obj-$(CONFIG_PINCTRL_MADERA) += pinctrl-madera.o

40
drivers/pinctrl/cirrus/pinctrl-cs47l15.c 100644
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L15
*
* Copyright (C) 2018-2019 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l15_aif1_pins[] = { 0, 1, 2, 3 };
static const unsigned int cs47l15_aif2_pins[] = { 4, 5, 6, 7 };
static const unsigned int cs47l15_aif3_pins[] = { 8, 9, 10, 11 };
static const unsigned int cs47l15_spk1_pins[] = { 12, 13, 14 };
static const struct madera_pin_groups cs47l15_pin_groups[] = {
{ "aif1", cs47l15_aif1_pins, ARRAY_SIZE(cs47l15_aif1_pins) },
{ "aif2", cs47l15_aif2_pins, ARRAY_SIZE(cs47l15_aif2_pins) },
{ "aif3", cs47l15_aif3_pins, ARRAY_SIZE(cs47l15_aif3_pins) },
{ "pdmspk1", cs47l15_spk1_pins, ARRAY_SIZE(cs47l15_spk1_pins) },
};
const struct madera_pin_chip cs47l15_pin_chip = {
.n_pins = CS47L15_NUM_GPIOS,
.pin_groups = cs47l15_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l15_pin_groups),
};

40
drivers/pinctrl/cirrus/pinctrl-cs47l92.c 100644
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl for Cirrus Logic CS47L92
*
* Copyright (C) 2018-2019 Cirrus Logic, Inc. and
* Cirrus Logic International Semiconductor Ltd.
*/
#include <linux/err.h>
#include <linux/mfd/madera/core.h>
#include "pinctrl-madera.h"
/*
* The alt func groups are the most commonly used functions we place these at
* the lower function indexes for convenience, and the less commonly used gpio
* functions at higher indexes.
*
* To stay consistent with the datasheet the function names are the same as
* the group names for that function's pins
*
* Note - all 1 less than in datasheet because these are zero-indexed
*/
static const unsigned int cs47l92_spk1_pins[] = { 2, 3 };
static const unsigned int cs47l92_aif1_pins[] = { 4, 5, 6, 7 };
static const unsigned int cs47l92_aif2_pins[] = { 8, 9, 10, 11 };
static const unsigned int cs47l92_aif3_pins[] = { 12, 13, 14, 15 };
static const struct madera_pin_groups cs47l92_pin_groups[] = {
{ "aif1", cs47l92_aif1_pins, ARRAY_SIZE(cs47l92_aif1_pins) },
{ "aif2", cs47l92_aif2_pins, ARRAY_SIZE(cs47l92_aif2_pins) },
{ "aif3", cs47l92_aif3_pins, ARRAY_SIZE(cs47l92_aif3_pins) },
{ "pdmspk1", cs47l92_spk1_pins, ARRAY_SIZE(cs47l92_spk1_pins) },
};
const struct madera_pin_chip cs47l92_pin_chip = {
.n_pins = CS47L92_NUM_GPIOS,
.pin_groups = cs47l92_pin_groups,
.n_pin_groups = ARRAY_SIZE(cs47l92_pin_groups),
};

24
drivers/pinctrl/cirrus/pinctrl-madera-core.c
View File

@ -396,6 +396,16 @@ static const struct {
.group_names = madera_pin_single_group_names,
.func = 0x157
},
{
.name = "aux-pdm-clk",
.group_names = madera_pin_single_group_names,
.func = 0x280
},
{
.name = "aux-pdm-dat",
.group_names = madera_pin_single_group_names,
.func = 0x281
},
};
static u16 madera_pin_make_drv_str(struct madera_pin_private *priv,
@ -986,7 +996,7 @@ static struct pinctrl_desc madera_pin_desc = {
static int madera_pin_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
const struct madera_pdata *pdata = dev_get_platdata(madera->dev);
const struct madera_pdata *pdata = &madera->pdata;
struct madera_pin_private *priv;
int ret;
@ -1004,6 +1014,10 @@ static int madera_pin_probe(struct platform_device *pdev)
pdev->dev.of_node = madera->dev->of_node;
switch (madera->type) {
case CS47L15:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L15))
priv->chip = &cs47l15_pin_chip;
break;
case CS47L35:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L35))
priv->chip = &cs47l35_pin_chip;
@ -1018,6 +1032,12 @@ static int madera_pin_probe(struct platform_device *pdev)
if (IS_ENABLED(CONFIG_PINCTRL_CS47L90))
priv->chip = &cs47l90_pin_chip;
break;
case CS42L92:
case CS47L92:
case CS47L93:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L92))
priv->chip = &cs47l92_pin_chip;
break;
default:
break;
}
@ -1037,7 +1057,7 @@ static int madera_pin_probe(struct platform_device *pdev)
}
/* if the configuration is provided through pdata, apply it */
if (pdata && pdata->gpio_configs) {
if (pdata->gpio_configs) {
ret = pinctrl_register_mappings(pdata->gpio_configs,
pdata->n_gpio_configs);
if (ret) {

2
drivers/pinctrl/cirrus/pinctrl-madera.h
View File

@ -30,8 +30,10 @@ struct madera_pin_private {
struct pinctrl_dev *pctl;
};
extern const struct madera_pin_chip cs47l15_pin_chip;
extern const struct madera_pin_chip cs47l35_pin_chip;
extern const struct madera_pin_chip cs47l85_pin_chip;
extern const struct madera_pin_chip cs47l90_pin_chip;
extern const struct madera_pin_chip cs47l92_pin_chip;
#endif

28
drivers/pinctrl/core.c
View File

@ -736,6 +736,34 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
return -EINVAL;
}
bool pinctrl_gpio_can_use_line(unsigned gpio)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range;
bool result;
int pin;
/*
* Try to obtain GPIO range, if it fails
* we're probably dealing with GPIO driver
* without a backing pin controller - bail out.
*/
if (pinctrl_get_device_gpio_range(gpio, &pctldev, &range))
return true;
mutex_lock(&pctldev->mutex);
/* Convert to the pin controllers number space */
pin = gpio_to_pin(range, gpio);
result = pinmux_can_be_used_for_gpio(pctldev, pin);
mutex_unlock(&pctldev->mutex);
return result;
}
EXPORT_SYMBOL_GPL(pinctrl_gpio_can_use_line);
/**
* pinctrl_gpio_request() - request a single pin to be used as GPIO
* @gpio: the GPIO pin number from the GPIO subsystem number space

6
drivers/pinctrl/devicetree.c
View File

@ -228,10 +228,8 @@ int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev)
* than dynamically allocate it and have to free it later,
* just point part way into the property name for the string.
*/
if (ret < 0) {
/* strlen("pinctrl-") == 8 */
statename = prop->name + 8;
}
if (ret < 0)
statename = prop->name + strlen("pinctrl-");
/* For every referenced pin configuration node in it */
for (config = 0; config < size; config++) {

13
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -672,8 +672,10 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
GFP_KERNEL);
if (!grp)
if (!grp) {
of_node_put(child);
return -ENOMEM;
}
mutex_lock(&ipctl->mutex);
radix_tree_insert(&pctl->pin_group_tree,
@ -697,12 +699,17 @@ static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
struct device_node *pinctrl_np;
for_each_child_of_node(np, function_np) {
if (of_property_read_bool(function_np, "fsl,pins"))
if (of_property_read_bool(function_np, "fsl,pins")) {
of_node_put(function_np);
return true;
}
for_each_child_of_node(function_np, pinctrl_np) {
if (of_property_read_bool(pinctrl_np, "fsl,pins"))
if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
of_node_put(pinctrl_np);
of_node_put(function_np);
return false;
}
}
}

12
drivers/pinctrl/freescale/pinctrl-mxs.c
View File

@ -488,8 +488,10 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
if (of_property_read_u32(child, "reg", &val)) {
ret = mxs_pinctrl_parse_group(pdev, child,
idxg++, NULL);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
continue;
}
@ -499,15 +501,19 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
f->ngroups,
sizeof(*f->groups),
GFP_KERNEL);
if (!f->groups)
if (!f->groups) {
of_node_put(child);
return -ENOMEM;
}
fn = child->name;
i = 0;
}
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
&f->groups[i++]);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
}
return 0;

67
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -98,13 +98,6 @@ struct byt_gpio_pin_context {
u32 val;
};
struct byt_community {
unsigned int pin_base;
size_t npins;
const unsigned int *pad_map;
void __iomem *reg_base;
};
#define COMMUNITY(p, n, map) \
{ \
.pin_base = (p), \
@ -112,26 +105,14 @@ struct byt_community {
.pad_map = (map),\
}
struct byt_pinctrl_soc_data {
const char *uid;
const struct pinctrl_pin_desc *pins;
size_t npins;
const struct intel_pingroup *groups;
size_t ngroups;
const struct intel_function *functions;
size_t nfunctions;
const struct byt_community *communities;
size_t ncommunities;
};
struct byt_gpio {
struct gpio_chip chip;
struct platform_device *pdev;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
raw_spinlock_t lock;
const struct byt_pinctrl_soc_data *soc_data;
struct byt_community *communities_copy;
const struct intel_pinctrl_soc_data *soc_data;
struct intel_community *communities_copy;
struct byt_gpio_pin_context *saved_context;
};
@ -383,11 +364,11 @@ static const struct intel_function byt_score_functions[] = {
FUNCTION("gpio", byt_score_gpio_groups),
};
static const struct byt_community byt_score_communities[] = {
static const struct intel_community byt_score_communities[] = {
COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
};
static const struct byt_pinctrl_soc_data byt_score_soc_data = {
static const struct intel_pinctrl_soc_data byt_score_soc_data = {
.uid = BYT_SCORE_ACPI_UID,
.pins = byt_score_pins,
.npins = ARRAY_SIZE(byt_score_pins),
@ -496,11 +477,11 @@ static const struct intel_function byt_sus_functions[] = {
FUNCTION("gpio", byt_sus_gpio_groups),
};
static const struct byt_community byt_sus_communities[] = {
static const struct intel_community byt_sus_communities[] = {
COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
};
static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
.uid = BYT_SUS_ACPI_UID,
.pins = byt_sus_pins,
.npins = ARRAY_SIZE(byt_sus_pins),
@ -549,11 +530,11 @@ static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
3, 6, 10, 13, 2, 5, 9, 7,
};
static const struct byt_community byt_ncore_communities[] = {
static const struct intel_community byt_ncore_communities[] = {
COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
};
static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
.uid = BYT_NCORE_ACPI_UID,
.pins = byt_ncore_pins,
.npins = ARRAY_SIZE(byt_ncore_pins),
@ -561,17 +542,17 @@ static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
.ncommunities = ARRAY_SIZE(byt_ncore_communities),
};
static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
&byt_score_soc_data,
&byt_sus_soc_data,
&byt_ncore_soc_data,
NULL
};
static struct byt_community *byt_get_community(struct byt_gpio *vg,
unsigned int pin)
static struct intel_community *byt_get_community(struct byt_gpio *vg,
unsigned int pin)
{
struct byt_community *comm;
struct intel_community *comm;
int i;
for (i = 0; i < vg->soc_data->ncommunities; i++) {
@ -586,7 +567,7 @@ static struct byt_community *byt_get_community(struct byt_gpio *vg,
static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
int reg)
{
struct byt_community *comm = byt_get_community(vg, offset);
struct intel_community *comm = byt_get_community(vg, offset);
u32 reg_offset;
if (!comm)
@ -605,7 +586,7 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
break;
}
return comm->reg_base + reg_offset + reg;
return comm->pad_regs + reg_offset + reg;
}
static int byt_get_groups_count(struct pinctrl_dev *pctldev)
@ -1211,7 +1192,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
u32 conf0, val;
for (i = 0; i < vg->soc_data->npins; i++) {
const struct byt_community *comm;
const struct intel_community *comm;
const char *pull_str = NULL;
const char *pull = NULL;
void __iomem *reg;
@ -1580,7 +1561,7 @@ static int byt_gpio_probe(struct byt_gpio *vg)
}
static int byt_set_soc_data(struct byt_gpio *vg,
const struct byt_pinctrl_soc_data *soc_data)
const struct intel_pinctrl_soc_data *soc_data)
{
int i;
@ -1593,15 +1574,13 @@ static int byt_set_soc_data(struct byt_gpio *vg,
return -ENOMEM;
for (i = 0; i < soc_data->ncommunities; i++) {
struct byt_community *comm = vg->communities_copy + i;
struct resource *mem_rc;
struct intel_community *comm = vg->communities_copy + i;
*comm = vg->soc_data->communities[i];
mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
if (IS_ERR(comm->reg_base))
return PTR_ERR(comm->reg_base);
comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);
if (IS_ERR(comm->pad_regs))
return PTR_ERR(comm->pad_regs);
}
return 0;
@ -1615,8 +1594,8 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = {
static int byt_pinctrl_probe(struct platform_device *pdev)
{
const struct byt_pinctrl_soc_data *soc_data = NULL;
const struct byt_pinctrl_soc_data **soc_table;
const struct intel_pinctrl_soc_data *soc_data = NULL;
const struct intel_pinctrl_soc_data **soc_table;
struct acpi_device *acpi_dev;
struct byt_gpio *vg;
int i, ret;
@ -1625,7 +1604,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
if (!acpi_dev)
return -ENODEV;
soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
for (i = 0; soc_table[i]; i++) {
if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {

4
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@ -15,8 +15,9 @@
#include "pinctrl-intel.h"
#define BXT_PAD_OWN 0x020
#define BXT_HOSTSW_OWN 0x080
#define BXT_PADCFGLOCK 0x060
#define BXT_HOSTSW_OWN 0x080
#define BXT_GPI_IS 0x100
#define BXT_GPI_IE 0x110
#define BXT_COMMUNITY(s, e) \
@ -24,6 +25,7 @@
.padown_offset = BXT_PAD_OWN, \
.padcfglock_offset = BXT_PADCFGLOCK, \
.hostown_offset = BXT_HOSTSW_OWN, \
.is_offset = BXT_GPI_IS, \
.ie_offset = BXT_GPI_IE, \
.gpp_size = 32, \
.pin_base = (s), \

2
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@ -19,6 +19,7 @@
#define CNL_PADCFGLOCK 0x080
#define CNL_LP_HOSTSW_OWN 0x0b0
#define CNL_H_HOSTSW_OWN 0x0c0
#define CNL_GPI_IS 0x100
#define CNL_GPI_IE 0x120
#define CNL_GPP(r, s, e, g) \
@ -37,6 +38,7 @@
.padown_offset = CNL_PAD_OWN, \
.padcfglock_offset = CNL_PADCFGLOCK, \
.hostown_offset = (o), \
.is_offset = CNL_GPI_IS, \
.ie_offset = CNL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \

8
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1677,7 +1677,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
{
struct chv_pinctrl *pctrl;
struct acpi_device *adev;
struct resource *res;
acpi_status status;
int ret, irq, i;
@ -1707,16 +1706,13 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
return -ENOMEM;
#endif
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pctrl->regs))
return PTR_ERR(pctrl->regs);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to get interrupt number\n");
if (irq < 0)
return irq;
}
pctrl->pctldesc = chv_pinctrl_desc;
pctrl->pctldesc.name = dev_name(&pdev->dev);

53
drivers/pinctrl/intel/pinctrl-denverton.c
View File

@ -15,8 +15,9 @@
#include "pinctrl-intel.h"
#define DNV_PAD_OWN 0x020
#define DNV_HOSTSW_OWN 0x0C0
#define DNV_PADCFGLOCK 0x090
#define DNV_HOSTSW_OWN 0x0C0
#define DNV_GPI_IS 0x100
#define DNV_GPI_IE 0x120
#define DNV_GPP(n, s, e) \
@ -32,6 +33,7 @@
.padown_offset = DNV_PAD_OWN, \
.padcfglock_offset = DNV_PADCFGLOCK, \
.hostown_offset = DNV_HOSTSW_OWN, \
.is_offset = DNV_GPI_IS, \
.ie_offset = DNV_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
@ -39,6 +41,7 @@
.ngpps = ARRAY_SIZE(g), \
}
/* Denverton */
static const struct pinctrl_pin_desc dnv_pins[] = {
/* North ALL */
PINCTRL_PIN(0, "GBE0_SDP0"),
@ -59,7 +62,7 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(15, "NCSI_CLK_IN"),
PINCTRL_PIN(16, "NCSI_RXD1"),
PINCTRL_PIN(17, "NCSI_CRS_DV"),
PINCTRL_PIN(18, "NCSI_ARB_IN"),
PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),
PINCTRL_PIN(19, "NCSI_TX_EN"),
PINCTRL_PIN(20, "NCSI_TXD0"),
PINCTRL_PIN(21, "NCSI_TXD1"),
@ -68,14 +71,14 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(24, "GBE0_LED1"),
PINCTRL_PIN(25, "GBE1_LED0"),
PINCTRL_PIN(26, "GBE1_LED1"),
PINCTRL_PIN(27, "GPIO_0"),
PINCTRL_PIN(27, "SPARE_0"),
PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
PINCTRL_PIN(33, "GPIO_1"),
PINCTRL_PIN(34, "GPIO_2"),
PINCTRL_PIN(33, "GBE_MDC"),
PINCTRL_PIN(34, "GBE_MDIO"),
PINCTRL_PIN(35, "SVID_ALERT_N"),
PINCTRL_PIN(36, "SVID_DATA"),
PINCTRL_PIN(37, "SVID_CLK"),
@ -102,15 +105,15 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(57, "DFX_PORT14"),
PINCTRL_PIN(58, "DFX_PORT15"),
/* South GPP0 */
PINCTRL_PIN(59, "GPIO_12"),
PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"),
PINCTRL_PIN(59, "SPI_TPM_CS_N"),
PINCTRL_PIN(60, "UART2_CTS"),
PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
PINCTRL_PIN(64, "UART0_RXD"),
PINCTRL_PIN(65, "UART0_TXD"),
PINCTRL_PIN(66, "SMB5_GBE_CLK"),
PINCTRL_PIN(67, "SMB5_GBE_DATA"),
PINCTRL_PIN(66, "CPU_RESET_N"),
PINCTRL_PIN(67, "NMI"),
PINCTRL_PIN(68, "ERROR2_N"),
PINCTRL_PIN(69, "ERROR1_N"),
PINCTRL_PIN(70, "ERROR0_N"),
@ -129,20 +132,20 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(83, "USB_OC0_N"),
PINCTRL_PIN(84, "FLEX_CLK_SE0"),
PINCTRL_PIN(85, "FLEX_CLK_SE1"),
PINCTRL_PIN(86, "GPIO_4"),
PINCTRL_PIN(87, "GPIO_5"),
PINCTRL_PIN(88, "GPIO_6"),
PINCTRL_PIN(89, "GPIO_7"),
PINCTRL_PIN(86, "SPARE_4"),
PINCTRL_PIN(87, "SMB3_IE0_CLK"),
PINCTRL_PIN(88, "SMB3_IE0_DATA"),
PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),
PINCTRL_PIN(90, "SATA0_LED_N"),
PINCTRL_PIN(91, "SATA1_LED_N"),
PINCTRL_PIN(92, "SATA_PDETECT0"),
PINCTRL_PIN(93, "SATA_PDETECT1"),
PINCTRL_PIN(94, "SATA0_SDOUT"),
PINCTRL_PIN(95, "SATA1_SDOUT"),
PINCTRL_PIN(94, "UART1_RTS"),
PINCTRL_PIN(95, "UART1_CTS"),
PINCTRL_PIN(96, "UART1_RXD"),
PINCTRL_PIN(97, "UART1_TXD"),
PINCTRL_PIN(98, "GPIO_8"),
PINCTRL_PIN(99, "GPIO_9"),
PINCTRL_PIN(98, "SPARE_8"),
PINCTRL_PIN(99, "SPARE_9"),
PINCTRL_PIN(100, "TCK"),
PINCTRL_PIN(101, "TRST_N"),
PINCTRL_PIN(102, "TMS"),
@ -150,11 +153,11 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(104, "TDO"),
PINCTRL_PIN(105, "CX_PRDY_N"),
PINCTRL_PIN(106, "CX_PREQ_N"),
PINCTRL_PIN(107, "CTBTRIGINOUT"),
PINCTRL_PIN(108, "CTBTRIGOUT"),
PINCTRL_PIN(109, "DFX_SPARE2"),
PINCTRL_PIN(110, "DFX_SPARE3"),
PINCTRL_PIN(111, "DFX_SPARE4"),
PINCTRL_PIN(107, "TAP1_TCK"),
PINCTRL_PIN(108, "TAP1_TRST_N"),
PINCTRL_PIN(109, "TAP1_TMS"),
PINCTRL_PIN(110, "TAP1_TDI"),
PINCTRL_PIN(111, "TAP1_TDO"),
/* South GPP1 */
PINCTRL_PIN(112, "SUSPWRDNACK"),
PINCTRL_PIN(113, "PMU_SUSCLK"),
@ -183,8 +186,8 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(136, "ESPI_CLK"),
PINCTRL_PIN(137, "ESPI_RST_N"),
PINCTRL_PIN(138, "ESPI_ALRT0_N"),
PINCTRL_PIN(139, "GPIO_10"),
PINCTRL_PIN(140, "GPIO_11"),
PINCTRL_PIN(139, "ESPI_CS1_N"),
PINCTRL_PIN(140, "ESPI_ALRT1_N"),
PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
PINCTRL_PIN(142, "EMMC_CMD"),
PINCTRL_PIN(143, "EMMC_STROBE"),
@ -197,7 +200,7 @@ static const struct pinctrl_pin_desc dnv_pins[] = {
PINCTRL_PIN(150, "EMMC_D5"),
PINCTRL_PIN(151, "EMMC_D6"),
PINCTRL_PIN(152, "EMMC_D7"),
PINCTRL_PIN(153, "GPIO_3"),
PINCTRL_PIN(153, "SPARE_3"),
};
static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };

2
drivers/pinctrl/intel/pinctrl-geminilake.c
View File

@ -17,6 +17,7 @@
#define GLK_PAD_OWN 0x020
#define GLK_PADCFGLOCK 0x080
#define GLK_HOSTSW_OWN 0x0b0
#define GLK_GPI_IS 0x100
#define GLK_GPI_IE 0x110
#define GLK_COMMUNITY(s, e) \
@ -24,6 +25,7 @@
.padown_offset = GLK_PAD_OWN, \
.padcfglock_offset = GLK_PADCFGLOCK, \
.hostown_offset = GLK_HOSTSW_OWN, \
.is_offset = GLK_GPI_IS, \
.ie_offset = GLK_GPI_IE, \
.gpp_size = 32, \
.pin_base = (s), \

2
drivers/pinctrl/intel/pinctrl-icelake.c
View File

@ -18,6 +18,7 @@
#define ICL_PAD_OWN 0x020
#define ICL_PADCFGLOCK 0x080
#define ICL_HOSTSW_OWN 0x0b0
#define ICL_GPI_IS 0x100
#define ICL_GPI_IE 0x110
#define ICL_GPP(r, s, e, g) \
@ -36,6 +37,7 @@
.padown_offset = ICL_PAD_OWN, \
.padcfglock_offset = ICL_PADCFGLOCK, \
.hostown_offset = ICL_HOSTSW_OWN, \
.is_offset = ICL_GPI_IS, \
.ie_offset = ICL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \

120
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -8,12 +8,13 @@
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/time.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@ -29,7 +30,6 @@
#define REVID_MASK GENMASK(31, 16)
#define PADBAR 0x00c
#define GPI_IS 0x100
#define PADOWN_BITS 4
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
@ -71,7 +71,7 @@
#define PADCFG2_DEBOUNCE_SHIFT 1
#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
#define DEBOUNCE_PERIOD 31250 /* ns */
#define DEBOUNCE_PERIOD_NSEC 31250
struct intel_pad_context {
u32 padcfg0;
@ -165,7 +165,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
padno = pin_to_padno(community, pin);
nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
if (reg >= nregs * 4)
return NULL;
return community->pad_regs + reg + padno * nregs * 4;
@ -220,47 +220,71 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
return !(readl(hostown) & BIT(gpp_offset));
}
static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
/**
* enum - Locking variants of the pad configuration
*
* @PAD_UNLOCKED: pad is fully controlled by the configuration registers
* @PAD_LOCKED: pad configuration registers, except TX state, are locked
* @PAD_LOCKED_TX: pad configuration TX state is locked
* @PAD_LOCKED_FULL: pad configuration registers are locked completely
*
* Locking is considered as read-only mode for corresponding registers and
* their respective fields. That said, TX state bit is locked separately from
* the main locking scheme.
*/
enum {
PAD_UNLOCKED = 0,
PAD_LOCKED = 1,
PAD_LOCKED_TX = 2,
PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
};
static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
{
struct intel_community *community;
const struct intel_padgroup *padgrp;
unsigned int offset, gpp_offset;
u32 value;
int ret = PAD_UNLOCKED;
community = intel_get_community(pctrl, pin);
if (!community)
return true;
return PAD_LOCKED_FULL;
if (!community->padcfglock_offset)
return false;
return PAD_UNLOCKED;
padgrp = intel_community_get_padgroup(community, pin);
if (!padgrp)
return true;
return PAD_LOCKED_FULL;
gpp_offset = padgroup_offset(padgrp, pin);
/*
* If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
* the pad is considered unlocked. Any other case means that it is
* either fully or partially locked and we don't touch it.
* either fully or partially locked.
*/
offset = community->padcfglock_offset + padgrp->reg_num * 8;
offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
value = readl(community->regs + offset);
if (value & BIT(gpp_offset))
return true;
ret |= PAD_LOCKED;
offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
value = readl(community->regs + offset);
if (value & BIT(gpp_offset))
return true;
ret |= PAD_LOCKED_TX;
return false;
return ret;
}
static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
{
return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
}
static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
{
return intel_pad_owned_by_host(pctrl, pin) &&
!intel_pad_locked(pctrl, pin);
return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
}
static int intel_get_groups_count(struct pinctrl_dev *pctldev)
@ -294,7 +318,8 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
void __iomem *padcfg;
u32 cfg0, cfg1, mode;
bool locked, acpi;
int locked;
bool acpi;
if (!intel_pad_owned_by_host(pctrl, pin)) {
seq_puts(s, "not available");
@ -322,11 +347,16 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
if (locked || acpi) {
seq_puts(s, " [");
if (locked) {
if (locked)
seq_puts(s, "LOCKED");
if (acpi)
seq_puts(s, ", ");
}
if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
seq_puts(s, " tx");
else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
seq_puts(s, " full");
if (locked && acpi)
seq_puts(s, ", ");
if (acpi)
seq_puts(s, "ACPI");
seq_puts(s, "]");
@ -448,11 +478,16 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
raw_spin_lock_irqsave(&pctrl->lock, flags);
if (!intel_pad_usable(pctrl, pin)) {
if (!intel_pad_owned_by_host(pctrl, pin)) {
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return -EBUSY;
}
if (!intel_pad_is_unlocked(pctrl, pin)) {
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
intel_gpio_set_gpio_mode(padcfg0);
/* Disable TX buffer and enable RX (this will be input) */
@ -566,7 +601,7 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
return -EINVAL;
v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
break;
}
@ -683,7 +718,7 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
if (debounce) {
unsigned long v;
v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
if (v < 3 || v > 15) {
ret = -EINVAL;
goto exit_unlock;
@ -796,6 +831,29 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
return -EINVAL;
}
/**
* intel_pin_to_gpio() - Translate from pin number to GPIO offset
* @pctrl: Pinctrl structure
* @pin: pin number
*
* Translate the pin number of pinctrl to GPIO offset
*/
static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
{
const struct intel_community *community;
const struct intel_padgroup *padgrp;
community = intel_get_community(pctrl, pin);
if (!community)
return -EINVAL;
padgrp = intel_community_get_padgroup(community, pin);
if (!padgrp)
return -EINVAL;
return pin - padgrp->base + padgrp->gpio_base;
}
static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
@ -1313,15 +1371,12 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
for (i = 0; i < pctrl->ncommunities; i++) {
struct intel_community *community = &pctrl->communities[i];
struct resource *res;
void __iomem *regs;
u32 padbar;
*community = pctrl->soc->communities[i];
res = platform_get_resource(pdev, IORESOURCE_MEM,
community->barno);
regs = devm_ioremap_resource(&pdev->dev, res);
regs = devm_platform_ioremap_resource(pdev, community->barno);
if (IS_ERR(regs))
return PTR_ERR(regs);
@ -1345,19 +1400,14 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
community->regs = regs;
community->pad_regs = regs + padbar;
if (!community->is_offset)
community->is_offset = GPI_IS;
ret = intel_pinctrl_add_padgroups(pctrl, community);
if (ret)
return ret;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to get interrupt number\n");
if (irq < 0)
return irq;
}
ret = intel_pinctrl_pm_init(pctrl);
if (ret)
@ -1421,8 +1471,6 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
table = (const struct intel_pinctrl_soc_data **)id->driver_data;
data = table[pdev->id];
}
if (!data)
return -ENODEV;
return intel_pinctrl_probe(pdev, data);
}
@ -1443,7 +1491,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int
* them alone.
*/
if (pd->mux_owner || pd->gpio_owner ||
gpiochip_line_is_irq(&pctrl->chip, pin))
gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
return true;
return false;

9
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -75,9 +75,9 @@ struct intel_padgroup {
* @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
* is assumed that the host owns the pin (rather than
* ACPI).
* @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
* default (%0x100).
* @is_offset: Register offset of GPI_IS from @regs.
* @ie_offset: Register offset of GPI_IE from @regs.
* @features: Additional features supported by the hardware
* @pin_base: Starting pin of pins in this community
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
* HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
@ -85,9 +85,9 @@ struct intel_padgroup {
* minimum. Use %0 if the number of registers can be
* determined by the size of the group.
* @npins: Number of pins in this community
* @features: Additional features supported by the hardware
* @gpps: Pad groups if the controller has variable size pad groups
* @ngpps: Number of pad groups in this community
* @pad_map: Optional non-linear mapping of the pads
* @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver)
*
@ -104,13 +104,14 @@ struct intel_community {
unsigned int hostown_offset;
unsigned int is_offset;
unsigned int ie_offset;
unsigned int features;
unsigned int pin_base;
unsigned int gpp_size;
unsigned int gpp_num_padown_regs;
size_t npins;
unsigned int features;
const struct intel_padgroup *gpps;
size_t ngpps;
const unsigned int *pad_map;
/* Reserved for the core driver */
void __iomem *regs;
void __iomem *pad_regs;

2
drivers/pinctrl/intel/pinctrl-lewisburg.c
View File

@ -17,6 +17,7 @@
#define LBG_PAD_OWN 0x020
#define LBG_PADCFGLOCK 0x060
#define LBG_HOSTSW_OWN 0x080
#define LBG_GPI_IS 0x100
#define LBG_GPI_IE 0x110
#define LBG_COMMUNITY(b, s, e) \
@ -25,6 +26,7 @@
.padown_offset = LBG_PAD_OWN, \
.padcfglock_offset = LBG_PADCFGLOCK, \
.hostown_offset = LBG_HOSTSW_OWN, \
.is_offset = LBG_GPI_IS, \
.ie_offset = LBG_GPI_IE, \
.gpp_size = 24, \
.pin_base = (s), \

4
drivers/pinctrl/intel/pinctrl-merrifield.c
View File

@ -885,7 +885,6 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev)
{
struct mrfld_family *families;
struct mrfld_pinctrl *mp;
struct resource *mem;
void __iomem *regs;
size_t nfamilies;
unsigned int i;
@ -897,8 +896,7 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev)
mp->dev = &pdev->dev;
raw_spin_lock_init(&mp->lock);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(&pdev->dev, mem);
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);

2
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -18,6 +18,7 @@
#define SPT_PAD_OWN 0x020
#define SPT_PADCFGLOCK 0x0a0
#define SPT_HOSTSW_OWN 0x0d0
#define SPT_GPI_IS 0x100
#define SPT_GPI_IE 0x120
#define SPT_COMMUNITY(b, s, e) \
@ -26,6 +27,7 @@
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
.gpp_size = 24, \
.gpp_num_padown_regs = 4, \

9
drivers/pinctrl/meson/pinctrl-meson-g12a.c
View File

@ -801,6 +801,9 @@ static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 };
/* ir_out */
static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 };
/* pwm_a_e */
static const unsigned int pwm_a_e_pins[] = { GPIOE_2 };
/* pwm_ao_a */
static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 };
static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 };
@ -888,6 +891,7 @@ static struct meson_pmx_group meson_g12a_aobus_groups[] = {
GROUP(i2c_ao_slave_sda, 3),
GROUP(remote_ao_input, 1),
GROUP(remote_ao_out, 1),
GROUP(pwm_a_e, 3),
GROUP(pwm_ao_a, 3),
GROUP(pwm_ao_a_hiz, 2),
GROUP(pwm_ao_b, 3),
@ -1192,6 +1196,10 @@ static const char * const remote_ao_out_groups[] = {
"remote_ao_out",
};
static const char * const pwm_a_e_groups[] = {
"pwm_a_e",
};
static const char * const pwm_ao_a_groups[] = {
"pwm_ao_a", "pwm_ao_a_hiz",
};
@ -1290,6 +1298,7 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = {
FUNCTION(i2c_ao_slave),
FUNCTION(remote_ao_input),
FUNCTION(remote_ao_out),
FUNCTION(pwm_a_e),
FUNCTION(pwm_ao_a),
FUNCTION(pwm_ao_b),
FUNCTION(pwm_ao_c),

12
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
View File

@ -192,8 +192,8 @@ static const unsigned int uart_rts_b_pins[] = { GPIODV_27 };
static const unsigned int uart_tx_c_pins[] = { GPIOY_13 };
static const unsigned int uart_rx_c_pins[] = { GPIOY_14 };
static const unsigned int uart_cts_c_pins[] = { GPIOX_11 };
static const unsigned int uart_rts_c_pins[] = { GPIOX_12 };
static const unsigned int uart_cts_c_pins[] = { GPIOY_11 };
static const unsigned int uart_rts_c_pins[] = { GPIOY_12 };
static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
@ -439,10 +439,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GROUP(pwm_f_x, 3, 18),
/* Bank Y */
GROUP(uart_cts_c, 1, 19),
GROUP(uart_rts_c, 1, 18),
GROUP(uart_tx_c, 1, 17),
GROUP(uart_rx_c, 1, 16),
GROUP(uart_cts_c, 1, 17),
GROUP(uart_rts_c, 1, 16),
GROUP(uart_tx_c, 1, 19),
GROUP(uart_rx_c, 1, 18),
GROUP(pwm_a_y, 1, 21),
GROUP(pwm_f_y, 1, 20),
GROUP(i2s_out_ch23_y, 1, 5),

1
drivers/pinctrl/meson/pinctrl-meson.c
View File

@ -651,6 +651,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
continue;
if (gpio_np) {
dev_err(pc->dev, "multiple gpio nodes\n");
of_node_put(np);
return -EINVAL;
}
gpio_np = np;

20
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
View File

@ -32,6 +32,7 @@ enum {
V_ARMADA_7K = BIT(0),
V_ARMADA_8K_CPM = BIT(1),
V_ARMADA_8K_CPS = BIT(2),
V_CP115_STANDALONE = BIT(3),
V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
};
@ -597,7 +598,8 @@ static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
MPP_FUNCTION(7, "uart0", "rxd"),
MPP_FUNCTION(8, "uart2", "rxd"),
MPP_FUNCTION(9, "sata0", "present_act"),
MPP_FUNCTION(10, "ge", "mdc")),
MPP_FUNCTION(10, "ge", "mdc"),
MPP_FUNCTION(14, "sdio", "ds")),
};
static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
@ -613,6 +615,10 @@ static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
.compatible = "marvell,armada-8k-cps-pinctrl",
.data = (void *) V_ARMADA_8K_CPS,
},
{
.compatible = "marvell,cp115-standalone-pinctrl",
.data = (void *) V_CP115_STANDALONE,
},
{ },
};
@ -654,16 +660,20 @@ static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
switch (i) {
case 0 ... 31:
mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPS);
mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPS |
V_CP115_STANDALONE));
break;
case 32 ... 38:
mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM |
V_CP115_STANDALONE));
break;
case 39 ... 43:
mvebu_pinctrl_assign_variant(m, V_ARMADA_8K_CPM);
mvebu_pinctrl_assign_variant(m, (V_ARMADA_8K_CPM |
V_CP115_STANDALONE));
break;
case 44 ... 62:
mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM |
V_CP115_STANDALONE));
break;
}
}

1
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -815,6 +815,7 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}

1
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -1508,6 +1508,7 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}

16
drivers/pinctrl/pinctrl-amd.c
View File

@ -565,15 +565,25 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
!(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
irq = irq_find_mapping(gc->irq.domain, irqnr + i);
generic_handle_irq(irq);
if (irq != 0)
generic_handle_irq(irq);
/* Clear interrupt.
* We must read the pin register again, in case the
* value was changed while executing
* generic_handle_irq() above.
* If we didn't find a mapping for the interrupt,
* disable it in order to avoid a system hang caused
* by an interrupt storm.
*/
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(regs + i);
if (irq == 0) {
regval &= ~BIT(INTERRUPT_ENABLE_OFF);
dev_dbg(&gpio_dev->pdev->dev,
"Disabling spurious GPIO IRQ %d\n",
irqnr + i);
}
writel(regval, regs + i);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
ret = IRQ_HANDLED;
@ -861,10 +871,8 @@ static int amd_gpio_probe(struct platform_device *pdev)
return -ENOMEM;
irq_base = platform_get_irq(pdev, 0);
if (irq_base < 0) {
dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
if (irq_base < 0)
return irq_base;
}
#ifdef CONFIG_PM_SLEEP
gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,

11
drivers/pinctrl/pinctrl-falcon.c
View File

@ -96,12 +96,8 @@ static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
int i;
for (i = 0; i < len; i++) {
/* strlen("ioXYZ") + 1 = 6 */
char *name = kzalloc(6, GFP_KERNEL);
snprintf(name, 6, "io%d", base + i);
d[i].number = base + i;
d[i].name = name;
d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
}
pad_count[bank] = len;
}
@ -455,12 +451,15 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
if (IS_ERR(falcon_info.clk[*bank])) {
dev_err(&ppdev->dev, "failed to get clock\n");
of_node_put(np)
return PTR_ERR(falcon_info.clk[*bank]);
}
falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
&res);
if (IS_ERR(falcon_info.membase[*bank]))
if (IS_ERR(falcon_info.membase[*bank])) {
of_node_put(np);
return PTR_ERR(falcon_info.membase[*bank]);
}
avail = pad_r32(falcon_info.membase[*bank],
LTQ_PADC_AVAIL);

755
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -3,6 +3,7 @@
* Ingenic SoCs pinctrl driver
*
* Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
* Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
*/
#include <linux/compiler.h>
@ -35,11 +36,14 @@
#define JZ4740_GPIO_TRIG 0x70
#define JZ4740_GPIO_FLAG 0x80
#define JZ4770_GPIO_INT 0x10
#define JZ4770_GPIO_PAT1 0x30
#define JZ4770_GPIO_PAT0 0x40
#define JZ4770_GPIO_FLAG 0x50
#define JZ4770_GPIO_PEN 0x70
#define JZ4760_GPIO_INT 0x10
#define JZ4760_GPIO_PAT1 0x30
#define JZ4760_GPIO_PAT0 0x40
#define JZ4760_GPIO_FLAG 0x50
#define JZ4760_GPIO_PEN 0x70
#define X1000_GPIO_PZ_BASE 0x700
#define X1000_GPIO_PZ_GID2LD 0x7f0
#define REG_SET(x) ((x) + 0x4)
#define REG_CLEAR(x) ((x) + 0x8)
@ -49,8 +53,13 @@
enum jz_version {
ID_JZ4740,
ID_JZ4725B,
ID_JZ4760,
ID_JZ4760B,
ID_JZ4770,
ID_JZ4780,
ID_X1000,
ID_X1000E,
ID_X1500,
};
struct ingenic_chip_info {
@ -338,6 +347,269 @@ static const struct ingenic_chip_info jz4725b_chip_info = {
.pull_downs = jz4740_pull_downs,
};
static const u32 jz4760_pull_ups[6] = {
0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
};
static const u32 jz4760_pull_downs[6] = {
0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
};
static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
static int jz4760_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int jz4760_nemc_16bit_data_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
static int jz4760_nemc_wait_pins[] = { 0x1b, };
static int jz4760_nemc_cs1_pins[] = { 0x15, };
static int jz4760_nemc_cs2_pins[] = { 0x16, };
static int jz4760_nemc_cs3_pins[] = { 0x17, };
static int jz4760_nemc_cs4_pins[] = { 0x18, };
static int jz4760_nemc_cs5_pins[] = { 0x19, };
static int jz4760_nemc_cs6_pins[] = { 0x1a, };
static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
static int jz4760_cim_pins[] = {
0x26, 0x27, 0x28, 0x29,
0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
};
static int jz4760_lcd_24bit_pins[] = {
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
0x58, 0x59, 0x5a, 0x5b,
};
static int jz4760_pwm_pwm0_pins[] = { 0x80, };
static int jz4760_pwm_pwm1_pins[] = { 0x81, };
static int jz4760_pwm_pwm2_pins[] = { 0x82, };
static int jz4760_pwm_pwm3_pins[] = { 0x83, };
static int jz4760_pwm_pwm4_pins[] = { 0x84, };
static int jz4760_pwm_pwm5_pins[] = { 0x85, };
static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
static int jz4760_uart0_data_funcs[] = { 0, 0, };
static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
static int jz4760_uart1_data_funcs[] = { 0, 0, };
static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
static int jz4760_uart2_data_funcs[] = { 0, 0, };
static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
static int jz4760_uart3_data_funcs[] = { 0, 1, };
static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
static int jz4760_nemc_wait_funcs[] = { 0, };
static int jz4760_nemc_cs1_funcs[] = { 0, };
static int jz4760_nemc_cs2_funcs[] = { 0, };
static int jz4760_nemc_cs3_funcs[] = { 0, };
static int jz4760_nemc_cs4_funcs[] = { 0, };
static int jz4760_nemc_cs5_funcs[] = { 0, };
static int jz4760_nemc_cs6_funcs[] = { 0, };
static int jz4760_i2c0_funcs[] = { 0, 0, };
static int jz4760_i2c1_funcs[] = { 0, 0, };
static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
static int jz4760_lcd_24bit_funcs[] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
};
static int jz4760_pwm_pwm0_funcs[] = { 0, };
static int jz4760_pwm_pwm1_funcs[] = { 0, };
static int jz4760_pwm_pwm2_funcs[] = { 0, };
static int jz4760_pwm_pwm3_funcs[] = { 0, };
static int jz4760_pwm_pwm4_funcs[] = { 0, };
static int jz4760_pwm_pwm5_funcs[] = { 0, };
static int jz4760_pwm_pwm6_funcs[] = { 0, };
static int jz4760_pwm_pwm7_funcs[] = { 0, };
static const struct group_desc jz4760_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
INGENIC_PIN_GROUP("cim-data", jz4760_cim),
INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
{ "lcd-no-pins", },
INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
};
static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4760_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a",
"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
};
static const char *jz4760_mmc1_groups[] = {
"mmc1-1bit-d", "mmc1-4bit-d",
"mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
};
static const char *jz4760_mmc2_groups[] = {
"mmc2-1bit-b", "mmc2-4bit-b",
"mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
};
static const char *jz4760_nemc_groups[] = {
"nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
"nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
};
static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
static const char *jz4760_cim_groups[] = { "cim-data", };
static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
static const char *jz4760_pwm0_groups[] = { "pwm0", };
static const char *jz4760_pwm1_groups[] = { "pwm1", };
static const char *jz4760_pwm2_groups[] = { "pwm2", };
static const char *jz4760_pwm3_groups[] = { "pwm3", };
static const char *jz4760_pwm4_groups[] = { "pwm4", };
static const char *jz4760_pwm5_groups[] = { "pwm5", };
static const char *jz4760_pwm6_groups[] = { "pwm6", };
static const char *jz4760_pwm7_groups[] = { "pwm7", };
static const struct function_desc jz4760_functions[] = {
{ "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
{ "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
{ "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
{ "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
{ "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
{ "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
{ "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
{ "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
{ "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
{ "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
{ "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
{ "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
{ "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
{ "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
{ "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
{ "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
{ "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
{ "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
{ "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
{ "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
{ "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
{ "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
{ "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
{ "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
{ "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
{ "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
};
static const struct ingenic_chip_info jz4760_chip_info = {
.num_chips = 6,
.groups = jz4760_groups,
.num_groups = ARRAY_SIZE(jz4760_groups),
.functions = jz4760_functions,
.num_functions = ARRAY_SIZE(jz4760_functions),
.pull_ups = jz4760_pull_ups,
.pull_downs = jz4760_pull_downs,
};
static const struct ingenic_chip_info jz4760b_chip_info = {
.num_chips = 6,
.groups = jz4760_groups,
.num_groups = ARRAY_SIZE(jz4760_groups),
.functions = jz4760_functions,
.num_functions = ARRAY_SIZE(jz4760_functions),
.pull_ups = jz4760_pull_ups,
.pull_downs = jz4760_pull_downs,
};
static const u32 jz4770_pull_ups[6] = {
0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
};
@ -744,6 +1016,320 @@ static const struct ingenic_chip_info jz4780_chip_info = {
.pull_downs = jz4770_pull_downs,
};
static const u32 x1000_pull_ups[4] = {
0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff,
};
static const u32 x1000_pull_downs[4] = {
0x00000000, 0x02000000, 0x02000000, 0x00000000,
};
static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
static int x1000_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
};
static int x1000_nemc_16bit_data_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int x1000_nemc_addr_pins[] = {
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
};
static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, };
static int x1000_nemc_wait_pins[] = { 0x34, };
static int x1000_nemc_cs1_pins[] = { 0x32, };
static int x1000_nemc_cs2_pins[] = { 0x33, };
static int x1000_i2c0_pins[] = { 0x38, 0x37, };
static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
static int x1000_i2c2_pins[] = { 0x61, 0x60, };
static int x1000_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
};
static int x1000_lcd_8bit_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x30, 0x31, 0x32, 0x33, 0x34,
};
static int x1000_lcd_16bit_pins[] = {
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
};
static int x1000_pwm_pwm0_pins[] = { 0x59, };
static int x1000_pwm_pwm1_pins[] = { 0x5a, };
static int x1000_pwm_pwm2_pins[] = { 0x5b, };
static int x1000_pwm_pwm3_pins[] = { 0x26, };
static int x1000_pwm_pwm4_pins[] = { 0x58, };
static int x1000_mac_pins[] = {
0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
};
static int x1000_uart0_data_funcs[] = { 0, 0, };
static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
static int x1000_uart1_data_a_funcs[] = { 2, 2, };
static int x1000_uart1_data_d_funcs[] = { 1, 1, };
static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, };
static int x1000_uart2_data_a_funcs[] = { 2, 2, };
static int x1000_uart2_data_d_funcs[] = { 0, 0, };
static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
static int x1000_nemc_addr_funcs[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
};
static int x1000_nemc_rd_we_funcs[] = { 0, 0, };
static int x1000_nemc_wait_funcs[] = { 0, };
static int x1000_nemc_cs1_funcs[] = { 0, };
static int x1000_nemc_cs2_funcs[] = { 0, };
static int x1000_i2c0_funcs[] = { 0, 0, };
static int x1000_i2c1_a_funcs[] = { 2, 2, };
static int x1000_i2c1_c_funcs[] = { 0, 0, };
static int x1000_i2c2_funcs[] = { 1, 1, };
static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
static int x1000_lcd_8bit_funcs[] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
static int x1000_pwm_pwm0_funcs[] = { 0, };
static int x1000_pwm_pwm1_funcs[] = { 1, };
static int x1000_pwm_pwm2_funcs[] = { 1, };
static int x1000_pwm_pwm3_funcs[] = { 2, };
static int x1000_pwm_pwm4_funcs[] = { 0, };
static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
static const struct group_desc x1000_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d),
INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data),
INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data),
INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr),
INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we),
INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait),
INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1),
INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2),
INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
INGENIC_PIN_GROUP("cim-data", x1000_cim),
INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
{ "lcd-no-pins", },
INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
INGENIC_PIN_GROUP("mac", x1000_mac),
};
static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x1000_uart1_groups[] = {
"uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
};
static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
static const char *x1000_mmc0_groups[] = {
"mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
};
static const char *x1000_mmc1_groups[] = {
"mmc1-1bit-e", "mmc1-4bit-e",
};
static const char *x1000_nemc_groups[] = {
"nemc-8bit-data", "nemc-16bit-data",
"nemc-addr", "nemc-rd-we", "nemc-wait",
};
static const char *x1000_cs1_groups[] = { "nemc-cs1", };
static const char *x1000_cs2_groups[] = { "nemc-cs2", };
static const char *x1000_i2c0_groups[] = { "i2c0-data", };
static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
static const char *x1000_i2c2_groups[] = { "i2c2-data", };
static const char *x1000_cim_groups[] = { "cim-data", };
static const char *x1000_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-no-pins",
};
static const char *x1000_pwm0_groups[] = { "pwm0", };
static const char *x1000_pwm1_groups[] = { "pwm1", };
static const char *x1000_pwm2_groups[] = { "pwm2", };
static const char *x1000_pwm3_groups[] = { "pwm3", };
static const char *x1000_pwm4_groups[] = { "pwm4", };
static const char *x1000_mac_groups[] = { "mac", };
static const struct function_desc x1000_functions[] = {
{ "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
{ "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
{ "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
{ "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
{ "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
{ "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), },
{ "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
{ "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
{ "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
{ "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
{ "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
{ "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
{ "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
{ "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
{ "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
{ "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
{ "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
{ "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
{ "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
};
static const struct ingenic_chip_info x1000_chip_info = {
.num_chips = 4,
.groups = x1000_groups,
.num_groups = ARRAY_SIZE(x1000_groups),
.functions = x1000_functions,
.num_functions = ARRAY_SIZE(x1000_functions),
.pull_ups = x1000_pull_ups,
.pull_downs = x1000_pull_downs,
};
static const struct ingenic_chip_info x1000e_chip_info = {
.num_chips = 4,
.groups = x1000_groups,
.num_groups = ARRAY_SIZE(x1000_groups),
.functions = x1000_functions,
.num_functions = ARRAY_SIZE(x1000_functions),
.pull_ups = x1000_pull_ups,
.pull_downs = x1000_pull_downs,
};
static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, };
static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
static int x1500_i2c0_pins[] = { 0x38, 0x37, };
static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
static int x1500_i2c2_pins[] = { 0x61, 0x60, };
static int x1500_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
};
static int x1500_pwm_pwm0_pins[] = { 0x59, };
static int x1500_pwm_pwm1_pins[] = { 0x5a, };
static int x1500_pwm_pwm2_pins[] = { 0x5b, };
static int x1500_pwm_pwm3_pins[] = { 0x26, };
static int x1500_pwm_pwm4_pins[] = { 0x58, };
static int x1500_uart0_data_funcs[] = { 0, 0, };
static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
static int x1500_uart1_data_a_funcs[] = { 2, 2, };
static int x1500_uart1_data_d_funcs[] = { 1, 1, };
static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, };
static int x1500_uart2_data_a_funcs[] = { 2, 2, };
static int x1500_uart2_data_d_funcs[] = { 0, 0, };
static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, };
static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, };
static int x1500_i2c0_funcs[] = { 0, 0, };
static int x1500_i2c1_a_funcs[] = { 2, 2, };
static int x1500_i2c1_c_funcs[] = { 0, 0, };
static int x1500_i2c2_funcs[] = { 1, 1, };
static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
static int x1500_pwm_pwm0_funcs[] = { 0, };
static int x1500_pwm_pwm1_funcs[] = { 1, };
static int x1500_pwm_pwm2_funcs[] = { 1, };
static int x1500_pwm_pwm3_funcs[] = { 2, };
static int x1500_pwm_pwm4_funcs[] = { 0, };
static const struct group_desc x1500_groups[] = {
INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d),
INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit),
INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit),
INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
INGENIC_PIN_GROUP("cim-data", x1500_cim),
{ "lcd-no-pins", },
INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
};
static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *x1500_uart1_groups[] = {
"uart1-data-a", "uart1-data-d", "uart1-hwflow-d",
};
static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
static const char *x1500_i2c0_groups[] = { "i2c0-data", };
static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
static const char *x1500_i2c2_groups[] = { "i2c2-data", };
static const char *x1500_cim_groups[] = { "cim-data", };
static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
static const char *x1500_pwm0_groups[] = { "pwm0", };
static const char *x1500_pwm1_groups[] = { "pwm1", };
static const char *x1500_pwm2_groups[] = { "pwm2", };
static const char *x1500_pwm3_groups[] = { "pwm3", };
static const char *x1500_pwm4_groups[] = { "pwm4", };
static const struct function_desc x1500_functions[] = {
{ "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
{ "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
{ "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
{ "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), },
{ "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
{ "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
{ "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
{ "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
{ "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
{ "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
{ "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
{ "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
{ "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
{ "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
};
static const struct ingenic_chip_info x1500_chip_info = {
.num_chips = 4,
.groups = x1500_groups,
.num_groups = ARRAY_SIZE(x1500_groups),
.functions = x1500_functions,
.num_functions = ARRAY_SIZE(x1500_functions),
.pull_ups = x1000_pull_ups,
.pull_downs = x1000_pull_downs,
};
static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
{
unsigned int val;
@ -764,6 +1350,23 @@ static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
}
static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
u8 reg, u8 offset, bool set)
{
if (set)
reg = REG_SET(reg);
else
reg = REG_CLEAR(reg);
regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset));
}
static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
{
regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD,
jzgc->gc.base / PINS_PER_GPIO_CHIP);
}
static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
u8 offset)
{
@ -775,8 +1378,8 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
u8 offset, int value)
{
if (jzgc->jzpc->version >= ID_JZ4770)
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
if (jzgc->jzpc->version >= ID_JZ4760)
ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
}
@ -786,9 +1389,9 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
{
u8 reg1, reg2;
if (jzgc->jzpc->version >= ID_JZ4770) {
reg1 = JZ4770_GPIO_PAT1;
reg2 = JZ4770_GPIO_PAT0;
if (jzgc->jzpc->version >= ID_JZ4760) {
reg1 = JZ4760_GPIO_PAT1;
reg2 = JZ4760_GPIO_PAT0;
} else {
reg1 = JZ4740_GPIO_TRIG;
reg2 = JZ4740_GPIO_DIR;
@ -796,21 +1399,45 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
switch (type) {
case IRQ_TYPE_EDGE_RISING:
ingenic_gpio_set_bit(jzgc, reg2, offset, true);
ingenic_gpio_set_bit(jzgc, reg1, offset, true);
if (jzgc->jzpc->version >= ID_X1000) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
ingenic_gpio_shadow_set_bit_load(jzgc);
} else {
ingenic_gpio_set_bit(jzgc, reg2, offset, true);
ingenic_gpio_set_bit(jzgc, reg1, offset, true);
}
break;
case IRQ_TYPE_EDGE_FALLING:
ingenic_gpio_set_bit(jzgc, reg2, offset, false);
ingenic_gpio_set_bit(jzgc, reg1, offset, true);
if (jzgc->jzpc->version >= ID_X1000) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true);
ingenic_gpio_shadow_set_bit_load(jzgc);
} else {
ingenic_gpio_set_bit(jzgc, reg2, offset, false);
ingenic_gpio_set_bit(jzgc, reg1, offset, true);
}
break;
case IRQ_TYPE_LEVEL_HIGH:
ingenic_gpio_set_bit(jzgc, reg2, offset, true);
ingenic_gpio_set_bit(jzgc, reg1, offset, false);
if (jzgc->jzpc->version >= ID_X1000) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
ingenic_gpio_shadow_set_bit_load(jzgc);
} else {
ingenic_gpio_set_bit(jzgc, reg2, offset, true);
ingenic_gpio_set_bit(jzgc, reg1, offset, false);
}
break;
case IRQ_TYPE_LEVEL_LOW:
default:
ingenic_gpio_set_bit(jzgc, reg2, offset, false);
ingenic_gpio_set_bit(jzgc, reg1, offset, false);
if (jzgc->jzpc->version >= ID_X1000) {
ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false);
ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false);
ingenic_gpio_shadow_set_bit_load(jzgc);
} else {
ingenic_gpio_set_bit(jzgc, reg2, offset, false);
ingenic_gpio_set_bit(jzgc, reg1, offset, false);
}
break;
}
}
@ -837,8 +1464,8 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
int irq = irqd->hwirq;
if (jzgc->jzpc->version >= ID_JZ4770)
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
if (jzgc->jzpc->version >= ID_JZ4760)
ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
@ -853,8 +1480,8 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd)
ingenic_gpio_irq_mask(irqd);
if (jzgc->jzpc->version >= ID_JZ4770)
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
if (jzgc->jzpc->version >= ID_JZ4760)
ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
}
@ -878,8 +1505,8 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd)
irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING);
}
if (jzgc->jzpc->version >= ID_JZ4770)
ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
if (jzgc->jzpc->version >= ID_JZ4760)
ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
else
ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
}
@ -935,8 +1562,8 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
chained_irq_enter(irq_chip, desc);
if (jzgc->jzpc->version >= ID_JZ4770)
flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
if (jzgc->jzpc->version >= ID_JZ4760)
flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
else
flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
@ -983,6 +1610,21 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
}
static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
unsigned int pin, u8 reg, bool set)
{
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
regmap_write(jzpc->map, X1000_GPIO_PZ_BASE +
(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
}
static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
unsigned int pin)
{
regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP);
}
static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
unsigned int pin, u8 reg)
{
@ -1001,8 +1643,8 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
struct ingenic_pinctrl *jzpc = jzgc->jzpc;
unsigned int pin = gc->base + offset;
if (jzpc->version >= ID_JZ4770)
return ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1);
if (jzpc->version >= ID_JZ4760)
return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1);
if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
return true;
@ -1027,11 +1669,17 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
'A' + offt, idx, func);
if (jzpc->version >= ID_JZ4770) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
if (jzpc->version >= ID_X1000) {
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
ingenic_shadow_config_pin_load(jzpc, pin);
} else if (jzpc->version >= ID_JZ4760) {
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
} else {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
@ -1080,10 +1728,15 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
'A' + offt, idx, input ? "in" : "out");
if (jzpc->version >= ID_JZ4770) {
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
if (jzpc->version >= ID_X1000) {
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
ingenic_shadow_config_pin_load(jzpc, pin);
} else if (jzpc->version >= ID_JZ4760) {
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
} else {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
@ -1110,8 +1763,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
bool pull;
if (jzpc->version >= ID_JZ4770)
pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
if (jzpc->version >= ID_JZ4760)
pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
else
pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
@ -1142,8 +1795,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
unsigned int pin, bool enabled)
{
if (jzpc->version >= ID_JZ4770)
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled);
if (jzpc->version >= ID_JZ4760)
ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled);
else
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
}
@ -1263,15 +1916,22 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = {
static const struct of_device_id ingenic_pinctrl_of_match[] = {
{ .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 },
{ .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B },
{ .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 },
{ .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B },
{ .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 },
{ .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 },
{ .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 },
{ .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E },
{ .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 },
{},
};
static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740-gpio", },
{ .compatible = "ingenic,jz4760-gpio", },
{ .compatible = "ingenic,jz4770-gpio", },
{ .compatible = "ingenic,jz4780-gpio", },
{ .compatible = "ingenic,x1000-gpio", },
{},
};
@ -1387,10 +2047,20 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
else
jzpc->version = (enum jz_version)id->driver_data;
if (jzpc->version >= ID_JZ4780)
if (jzpc->version >= ID_X1500)
chip_info = &x1500_chip_info;
else if (jzpc->version >= ID_X1000E)
chip_info = &x1000e_chip_info;
else if (jzpc->version >= ID_X1000)
chip_info = &x1000_chip_info;
else if (jzpc->version >= ID_JZ4780)
chip_info = &jz4780_chip_info;
else if (jzpc->version >= ID_JZ4770)
chip_info = &jz4770_chip_info;
else if (jzpc->version >= ID_JZ4760B)
chip_info = &jz4760b_chip_info;
else if (jzpc->version >= ID_JZ4760)
chip_info = &jz4760_chip_info;
else if (jzpc->version >= ID_JZ4725B)
chip_info = &jz4725b_chip_info;
else
@ -1467,8 +2137,13 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
static const struct platform_device_id ingenic_pinctrl_ids[] = {
{ "jz4740-pinctrl", ID_JZ4740 },
{ "jz4725b-pinctrl", ID_JZ4725B },
{ "jz4760-pinctrl", ID_JZ4760 },
{ "jz4760b-pinctrl", ID_JZ4760B },
{ "jz4770-pinctrl", ID_JZ4770 },
{ "jz4780-pinctrl", ID_JZ4780 },
{ "x1000-pinctrl", ID_X1000 },
{ "x1000e-pinctrl", ID_X1000E },
{ "x1500-pinctrl", ID_X1500 },
{},
};

8
drivers/pinctrl/pinctrl-oxnas.c
View File

@ -902,7 +902,6 @@ static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
unsigned int param;
u32 arg;
unsigned int i;
u32 offset = pin - bank->gpio_chip.base;
u32 mask = BIT(offset);
@ -912,7 +911,6 @@ static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
@ -941,7 +939,6 @@ static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
unsigned int param;
u32 arg;
unsigned int i;
u32 offset = pin - bank->gpio_chip.base;
u32 mask = BIT(offset);
@ -951,7 +948,6 @@ static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
@ -1229,10 +1225,8 @@ static int oxnas_gpio_probe(struct platform_device *pdev)
return PTR_ERR(bank->reg_base);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "irq get failed\n");
if (irq < 0)
return irq;
}
bank->id = id;
bank->gpio_chip.parent = &pdev->dev;

4
drivers/pinctrl/pinctrl-pic32.c
View File

@ -2222,10 +2222,8 @@ static int pic32_gpio_probe(struct platform_device *pdev)
return PTR_ERR(bank->reg_base);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "irq get failed\n");
if (irq < 0)
return irq;
}
bank->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(bank->clk)) {

4
drivers/pinctrl/pinctrl-rk805.c
View File

@ -197,7 +197,7 @@ static int rk805_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
return !(val & pci->pin_cfg[offset].dir_msk);
}
static struct gpio_chip rk805_gpio_chip = {
static const struct gpio_chip rk805_gpio_chip = {
.label = "rk805-gpio",
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
@ -404,7 +404,7 @@ static const struct pinconf_ops rk805_pinconf_ops = {
.pin_config_set = rk805_pinconf_set,
};
static struct pinctrl_desc rk805_pinctrl_desc = {
static const struct pinctrl_desc rk805_pinctrl_desc = {
.name = "rk805-pinctrl",
.pctlops = &rk805_pinctrl_ops,
.pmxops = &rk805_pinmux_ops,

1
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -2792,6 +2792,7 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
* still return -ENOTSUPP as before, to make sure the caller
* of gpiod_set_debounce won't change its behaviour.
*/
return -ENOTSUPP;
default:
return -ENOTSUPP;
}

16
drivers/pinctrl/pinctrl-rza1.c
View File

@ -866,8 +866,10 @@ static int rza1_dt_node_pin_count(struct device_node *np)
npins = 0;
for_each_child_of_node(np, child) {
of_pins = of_find_property(child, "pinmux", NULL);
if (!of_pins)
if (!of_pins) {
of_node_put(child);
return -EINVAL;
}
npins += of_pins->length / sizeof(u32);
}
@ -1025,8 +1027,10 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
for_each_child_of_node(np, child) {
ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
grpin);
if (ret < 0)
if (ret < 0) {
of_node_put(child);
return ret;
}
grpin += ret;
mux_conf += ret;
@ -1272,8 +1276,10 @@ static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
&gpio_ranges[i]);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
++i;
}
@ -1359,7 +1365,6 @@ static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
static int rza1_pinctrl_probe(struct platform_device *pdev)
{
struct rza1_pinctrl *rza1_pctl;
struct resource *res;
int ret;
rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
@ -1368,8 +1373,7 @@ static int rza1_pinctrl_probe(struct platform_device *pdev)
rza1_pctl->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rza1_pctl->base))
return PTR_ERR(rza1_pctl->base);

17
drivers/pinctrl/pinctrl-rza2.c
View File

@ -11,7 +11,8 @@
*/
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinmux.h>
@ -115,7 +116,7 @@ static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
if (dir == GPIOF_DIR_IN)
if (dir)
reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
else
reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
@ -134,18 +135,18 @@ static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
if (reg16 == RZA2_PDR_OUTPUT)
return GPIOF_DIR_OUT;
return 0;
if (reg16 == RZA2_PDR_INPUT)
return GPIOF_DIR_IN;
return 1;
/*
* This GPIO controller has a default Hi-Z state that is not input or
* output, so force the pin to input now.
*/
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
rza2_pin_to_gpio(priv->base, offset, 1);
return GPIOF_DIR_IN;
return 1;
}
static int rza2_chip_direction_input(struct gpio_chip *chip,
@ -153,7 +154,7 @@ static int rza2_chip_direction_input(struct gpio_chip *chip,
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
rza2_pin_to_gpio(priv->base, offset, 1);
return 0;
}
@ -191,7 +192,7 @@ static int rza2_chip_direction_output(struct gpio_chip *chip,
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_chip_set(chip, offset, val);
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT);
rza2_pin_to_gpio(priv->base, offset, 0);
return 0;
}

12
drivers/pinctrl/pinctrl-rzn1.c
View File

@ -412,8 +412,10 @@ static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
for_each_child_of_node(np, child) {
ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
if (ret < 0)
if (ret < 0) {
of_node_put(child);
return ret;
}
}
return 0;
@ -792,8 +794,10 @@ static int rzn1_pinctrl_parse_functions(struct device_node *np,
grp = &ipctl->groups[ipctl->ngroups];
grp->func = func->name;
ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
if (ret < 0)
if (ret < 0) {
of_node_put(child);
return ret;
}
i++;
ipctl->ngroups++;
}
@ -838,8 +842,10 @@ static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
for_each_child_of_node(np, child) {
ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
if (ret < 0)
if (ret < 0) {
of_node_put(child);
return ret;
}
}
return 0;

12
drivers/pinctrl/pinctrl-st.c
View File

@ -12,8 +12,9 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_gpio.h>
#include <linux/of_gpio.h> /* of_get_named_gpio() */
#include <linux/of_address.h>
#include <linux/gpio/driver.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/pinctrl.h>
@ -1262,8 +1263,10 @@ static int st_pctl_parse_functions(struct device_node *np,
grp = &info->groups[*grp_index];
*grp_index += 1;
ret = st_pctl_dt_parse_groups(child, grp, info, i++);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
}
dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
index, func->name, func->ngroups);
@ -1623,8 +1626,10 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
if (of_property_read_bool(child, "gpio-controller")) {
const char *bank_name = NULL;
ret = st_gpiolib_register_bank(info, bank, child);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
k = info->banks[bank].range.pin_base;
bank_name = info->banks[bank].range.name;
@ -1641,6 +1646,7 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
i++, &grp_index);
if (ret) {
dev_err(&pdev->dev, "No functions found.\n");
of_node_put(child);
return ret;
}
}

28
drivers/pinctrl/pinctrl-stmfx.c
View File

@ -296,29 +296,29 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
switch (param) {
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_DRIVE_PUSH_PULL:
ret = stmfx_pinconf_set_type(pctl, pin, 0);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
ret = stmfx_pinconf_set_type(pctl, pin, 1);
if (ret)
return ret;
ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
if (ret)
return ret;
break;
case PIN_CONFIG_BIAS_PULL_UP:
ret = stmfx_pinconf_set_type(pctl, pin, 1);
if (ret)
return ret;
ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
if (ret)
return ret;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!dir)
ret = stmfx_pinconf_set_type(pctl, pin, 1);
else
ret = stmfx_pinconf_set_type(pctl, pin, 0);
if (ret)
return ret;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (!dir)
ret = stmfx_pinconf_set_type(pctl, pin, 0);
else
ret = stmfx_pinconf_set_type(pctl, pin, 1);
ret = stmfx_pinconf_set_type(pctl, pin, 1);
if (ret)
return ret;
break;
@ -620,10 +620,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev)
}
irq = platform_get_irq(pdev, 0);
if (irq <= 0) {
dev_err(pctl->dev, "failed to get irq\n");
if (irq <= 0)
return -ENXIO;
}
mutex_init(&pctl->lock);

4
drivers/pinctrl/pinctrl-xway.c
View File

@ -1731,13 +1731,11 @@ static int pinmux_xway_probe(struct platform_device *pdev)
return -ENOMEM;
for (i = 0; i < xway_chip.ngpio; i++) {
/* strlen("ioXY") + 1 = 5 */
char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i);
if (!name)
return -ENOMEM;
snprintf(name, 5, "io%d", i);
xway_info.pads[i].number = GPIO0 + i;
xway_info.pads[i].name = name;
}

24
drivers/pinctrl/pinmux.c
View File

@ -70,6 +70,30 @@ int pinmux_validate_map(const struct pinctrl_map *map, int i)
return 0;
}
/**
* pinmux_can_be_used_for_gpio() - check if a specific pin
* is either muxed to a different function or used as gpio.
*
* @pin: the pin number in the global pin space
*
* Controllers not defined as strict will always return true,
* menaning that the gpio can be used.
*/
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin)
{
struct pin_desc *desc = pin_desc_get(pctldev, pin);
const struct pinmux_ops *ops = pctldev->desc->pmxops;
/* Can't inspect pin, assume it can be used */
if (!desc)
return true;
if (ops->strict && desc->mux_usecount)
return false;
return !(ops->strict && !!desc->gpio_owner);
}
/**
* pin_request() - request a single pin to be muxed in, typically for GPIO
* @pin: the pin number in the global pin space

8
drivers/pinctrl/pinmux.h
View File

@ -15,6 +15,8 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev);
int pinmux_validate_map(const struct pinctrl_map *map, int i);
bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin);
int pinmux_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin, unsigned gpio);
@ -42,6 +44,12 @@ static inline int pinmux_validate_map(const struct pinctrl_map *map, int i)
return 0;
}
static inline bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev,
unsigned pin)
{
return true;
}
static inline int pinmux_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin, unsigned gpio)

9
drivers/pinctrl/qcom/Kconfig
View File

@ -159,6 +159,15 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
config PINCTRL_SC7180
tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7180 platform.
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on GPIOLIB && OF

1
drivers/pinctrl/qcom/Makefile
View File

@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o

36
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -618,8 +618,7 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
}
/* The number of GPIOs in the ACPI tables */
len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
0);
len = ret = device_property_count_u16(pctrl->dev, "gpios");
if (ret < 0)
return 0;
@ -996,12 +995,13 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
if (pctrl->soc->reserved_gpios)
return true;
return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
return device_property_count_u16(pctrl->dev, "gpios") > 0;
}
static int msm_gpio_init(struct msm_pinctrl *pctrl)
{
struct gpio_chip *chip;
struct gpio_irq_chip *girq;
int ret;
unsigned ngpio = pctrl->soc->ngpios;
@ -1028,6 +1028,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
girq = &chip->irq;
girq->chip = &pctrl->irq_chip;
girq->parent_handler = msm_gpio_irq_handler;
girq->num_parents = 1;
girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
GFP_KERNEL);
if (!girq->parents)
return -ENOMEM;
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_bad_irq;
girq->parents[0] = pctrl->irq;
ret = gpiochip_add_data(&pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "Failed register gpiochip\n");
@ -1054,20 +1066,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
}
}
ret = gpiochip_irqchip_add(chip,
&pctrl->irq_chip,
0,
handle_edge_irq,
IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
gpiochip_remove(&pctrl->chip);
return -ENOSYS;
}
gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
msm_gpio_irq_handler);
return 0;
}
@ -1161,10 +1159,8 @@ int msm_pinctrl_probe(struct platform_device *pdev,
msm_pinctrl_setup_pm_reset(pctrl);
pctrl->irq = platform_get_irq(pdev, 0);
if (pctrl->irq < 0) {
dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
if (pctrl->irq < 0)
return pctrl->irq;
}
pctrl->desc.owner = THIS_MODULE;
pctrl->desc.pctlops = &msm_pinctrl_ops;

76
drivers/pinctrl/qcom/pinctrl-msm8998.c
View File

@ -581,16 +581,8 @@ enum msm8998_functions {
msm_mux_tgu_ch1,
msm_mux_tsense_pwm1,
msm_mux_tsense_pwm2,
msm_mux_tsif1_clk,
msm_mux_tsif1_data,
msm_mux_tsif1_en,
msm_mux_tsif1_error,
msm_mux_tsif1_sync,
msm_mux_tsif2_clk,
msm_mux_tsif2_data,
msm_mux_tsif2_en,
msm_mux_tsif2_error,
msm_mux_tsif2_sync,
msm_mux_tsif0,
msm_mux_tsif1,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
@ -692,9 +684,6 @@ static const char * const atest_usb13_groups[] = {
static const char * const bimc_dte1_groups[] = {
"gpio8", "gpio10",
};
static const char * const tsif1_sync_groups[] = {
"gpio9",
};
static const char * const wlan1_adc0_groups[] = {
"gpio9",
};
@ -863,9 +852,6 @@ static const char * const lpass_slimbus_groups[] = {
static const char * const sd_write_groups[] = {
"gpio40",
};
static const char * const tsif1_error_groups[] = {
"gpio40",
};
static const char * const blsp_spi6_groups[] = {
"gpio41", "gpio42", "gpio43", "gpio44",
};
@ -1048,11 +1034,8 @@ static const char * const blsp_uim2_b_groups[] = {
static const char * const blsp_i2c5_groups[] = {
"gpio87", "gpio88",
};
static const char * const tsif1_clk_groups[] = {
"gpio89",
};
static const char * const tsif1_en_groups[] = {
"gpio90",
static const char * const tsif0_groups[] = {
"gpio9", "gpio40", "gpio89", "gpio90", "gpio91",
};
static const char * const mdp_vsync0_groups[] = {
"gpio90",
@ -1075,17 +1058,14 @@ static const char * const tgu_ch0_groups[] = {
static const char * const qdss_cti1_b_groups[] = {
"gpio90", "gpio91",
};
static const char * const tsif1_data_groups[] = {
"gpio91",
};
static const char * const sdc4_cmd_groups[] = {
"gpio91",
};
static const char * const tgu_ch1_groups[] = {
"gpio91",
};
static const char * const tsif2_error_groups[] = {
"gpio92",
static const char * const tsif1_groups[] = {
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
};
static const char * const sdc43_groups[] = {
"gpio92",
@ -1093,30 +1073,18 @@ static const char * const sdc43_groups[] = {
static const char * const vfr_1_groups[] = {
"gpio92",
};
static const char * const tsif2_clk_groups[] = {
"gpio93",
};
static const char * const sdc4_clk_groups[] = {
"gpio93",
};
static const char * const tsif2_en_groups[] = {
"gpio94",
};
static const char * const sdc42_groups[] = {
"gpio94",
};
static const char * const sd_card_groups[] = {
"gpio95",
};
static const char * const tsif2_data_groups[] = {
"gpio95",
};
static const char * const sdc41_groups[] = {
"gpio95",
};
static const char * const tsif2_sync_groups[] = {
"gpio96",
};
static const char * const sdc40_groups[] = {
"gpio96",
};
@ -1355,16 +1323,8 @@ static const struct msm_function msm8998_functions[] = {
FUNCTION(tgu_ch1),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif1_clk),
FUNCTION(tsif1_data),
FUNCTION(tsif1_en),
FUNCTION(tsif1_error),
FUNCTION(tsif1_sync),
FUNCTION(tsif2_clk),
FUNCTION(tsif2_data),
FUNCTION(tsif2_en),
FUNCTION(tsif2_error),
FUNCTION(tsif2_sync),
FUNCTION(tsif0),
FUNCTION(tsif1),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
@ -1396,7 +1356,7 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
@ -1427,7 +1387,7 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
PINGROUP(40, EAST, sd_write, tsif1_error, _, _, _, _, _, _, _),
PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _),
PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
@ -1476,14 +1436,14 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
PINGROUP(89, EAST, tsif1_clk, phase_flag, _, _, _, _, _, _, _),
PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag, _, _, _, _, _),
PINGROUP(93, EAST, tsif2_clk, sdc4_clk, _, qdss, _, _, _, _, _),
PINGROUP(94, EAST, tsif2_en, sdc42, _, _, _, _, _, _, _),
PINGROUP(95, EAST, tsif2_data, sdc41, _, _, _, _, _, _, _),
PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag, _, _, _, _, _, _),
PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _),
PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _),
PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _),
PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _),
PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _),
PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _),
PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),

2
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
View File

@ -52,7 +52,7 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
}
/* The number of GPIOs in the approved list */
ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
ret = device_property_count_u8(&pdev->dev, "gpios");
if (ret < 0) {
dev_err(&pdev->dev, "missing 'gpios' property\n");
return ret;

1146
drivers/pinctrl/qcom/pinctrl-sc7180.c 100644
View File

File diff suppressed because it is too large Load Diff

8
drivers/pinctrl/qcom/pinctrl-sdm845.c
View File

@ -262,10 +262,10 @@ static const struct pinctrl_pin_desc sdm845_pins[] = {
PINCTRL_PIN(147, "GPIO_147"),
PINCTRL_PIN(148, "GPIO_148"),
PINCTRL_PIN(149, "GPIO_149"),
PINCTRL_PIN(150, "SDC2_CLK"),
PINCTRL_PIN(151, "SDC2_CMD"),
PINCTRL_PIN(152, "SDC2_DATA"),
PINCTRL_PIN(153, "UFS_RESET"),
PINCTRL_PIN(150, "UFS_RESET"),
PINCTRL_PIN(151, "SDC2_CLK"),
PINCTRL_PIN(152, "SDC2_CMD"),
PINCTRL_PIN(153, "SDC2_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \

8
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -793,11 +793,13 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
switch (subtype) {
case PMIC_GPIO_SUBTYPE_GPIO_4CH:
pad->have_buffer = true;
/* Fall through */
case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
pad->num_sources = 4;
break;
case PMIC_GPIO_SUBTYPE_GPIO_8CH:
pad->have_buffer = true;
/* Fall through */
case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
pad->num_sources = 8;
break;
@ -1113,6 +1115,12 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
/* pm8150l has 12 GPIOs with holes on 7 */
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
{ },
};

5
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
View File

@ -791,11 +791,8 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev)
for (i = 0; i < pctrl->desc.npins; i++) {
pin_data[i].reg = SSBI_REG_ADDR_MPP(i);
pin_data[i].irq = platform_get_irq(pdev, i);
if (pin_data[i].irq < 0) {
dev_err(&pdev->dev,
"missing interrupts for pin %d\n", i);
if (pin_data[i].irq < 0)
return pin_data[i].irq;
}
ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
if (ret)

11
drivers/pinctrl/sh-pfc/gpio.c
View File

@ -7,7 +7,7 @@
*/
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
@ -255,18 +255,13 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
static bool __print_once;
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
int ret;
if (!__print_once) {
dev_notice(pfc->dev,
"Use of GPIO API for function requests is deprecated."
" Convert to pinctrl\n");
__print_once = true;
}
dev_notice_once(pfc->dev,
"Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
if (mark == 0)
return -EINVAL;

43
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -26,7 +26,9 @@
#include "../pinconf.h"
struct sh_pfc_pin_config {
u32 type;
unsigned int mux_mark;
bool mux_set;
bool gpio_enabled;
};
struct sh_pfc_pinctrl {
@ -355,16 +357,27 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
if (cfg->type != PINMUX_TYPE_NONE) {
/*
* This driver cannot manage both gpio and mux when the gpio
* pin is already enabled. So, this function fails.
*/
if (cfg->gpio_enabled) {
ret = -EBUSY;
goto done;
}
}
for (i = 0; i < grp->nr_pins; ++i) {
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
goto done;
}
/* All group pins are configured, mark the pins as mux_set */
for (i = 0; i < grp->nr_pins; ++i) {
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
cfg->mux_set = true;
cfg->mux_mark = grp->mux[i];
}
done:
@ -385,14 +398,6 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pfc->lock, flags);
if (cfg->type != PINMUX_TYPE_NONE) {
dev_err(pfc->dev,
"Pin %u is busy, can't configure it as GPIO.\n",
offset);
ret = -EBUSY;
goto done;
}
if (!pfc->gpio) {
/* If GPIOs are handled externally the pin mux type need to be
* set to GPIO here.
@ -404,7 +409,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
goto done;
}
cfg->type = PINMUX_TYPE_GPIO;
cfg->gpio_enabled = true;
ret = 0;
@ -425,7 +430,10 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
unsigned long flags;
spin_lock_irqsave(&pfc->lock, flags);
cfg->type = PINMUX_TYPE_NONE;
cfg->gpio_enabled = false;
/* If mux is already set, this configures it here */
if (cfg->mux_set)
sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
spin_unlock_irqrestore(&pfc->lock, flags);
}
@ -438,7 +446,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
int idx = sh_pfc_get_pin_index(pfc, offset);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
unsigned int dir;
int ret;
@ -458,8 +465,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
if (ret < 0)
goto done;
cfg->type = new_type;
done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
@ -782,13 +787,11 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
for (i = 0; i < pfc->info->nr_pins; ++i) {
const struct sh_pfc_pin *info = &pfc->info->pins[i];
struct sh_pfc_pin_config *cfg = &pmx->configs[i];
struct pinctrl_pin_desc *pin = &pmx->pins[i];
/* If the pin number is equal to -1 all pins are considered */
pin->number = info->pin != (u16)-1 ? info->pin : i;
pin->name = info->name;
cfg->type = PINMUX_TYPE_NONE;
}
return 0;

8
drivers/pinctrl/spear/pinctrl-spear.c
View File

@ -157,12 +157,16 @@ static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
/* calculate number of maps required */
for_each_child_of_node(np_config, np) {
ret = of_property_read_string(np, "st,function", &function);
if (ret < 0)
if (ret < 0) {
of_node_put(np);
return ret;
}
ret = of_property_count_strings(np, "st,pins");
if (ret < 0)
if (ret < 0) {
of_node_put(np);
return ret;
}
count += ret;
}

1
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
View File

@ -940,7 +940,6 @@ MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
static struct platform_driver sprd_pinctrl_driver = {
.driver = {
.name = "sprd-pinctrl",
.owner = THIS_MODULE,
.of_match_table = sprd_pinctrl_of_match,
},
.probe = sprd_pinctrl_probe,

32
drivers/pinctrl/sprd/pinctrl-sprd.c
View File

@ -454,7 +454,7 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
if (pin->type == GLOBAL_CTRL_PIN &&
param == SPRD_PIN_CONFIG_CONTROL) {
arg = reg;
} else if (pin->type == COMMON_PIN) {
} else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
switch (param) {
case SPRD_PIN_CONFIG_SLEEP_MODE:
arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
@ -465,14 +465,6 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
case PIN_CONFIG_OUTPUT:
arg = reg & SLEEP_OUTPUT_MASK;
break;
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
arg = 0;
break;
default:
return -ENOTSUPP;
}
} else if (pin->type == MISC_PIN) {
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
arg = (reg >> DRIVE_STRENGTH_SHIFT) &
DRIVE_STRENGTH_MASK;
@ -606,7 +598,7 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
if (pin->type == GLOBAL_CTRL_PIN &&
param == SPRD_PIN_CONFIG_CONTROL) {
val = arg;
} else if (pin->type == COMMON_PIN) {
} else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
switch (param) {
case SPRD_PIN_CONFIG_SLEEP_MODE:
if (arg & AP_SLEEP)
@ -639,13 +631,6 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
shift = SLEEP_OUTPUT_SHIFT;
}
break;
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
continue;
default:
return -ENOTSUPP;
}
} else if (pin->type == MISC_PIN) {
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
if (arg < 2 || arg > 60)
return -EINVAL;
@ -940,8 +925,10 @@ static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
for_each_child_of_node(np, child) {
ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
*temp++ = grp->name;
grp++;
@ -950,8 +937,11 @@ static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
for_each_child_of_node(child, sub_child) {
ret = sprd_pinctrl_parse_groups(sub_child,
sprd_pctl, grp);
if (ret)
if (ret) {
of_node_put(sub_child);
of_node_put(child);
return ret;
}
*temp++ = grp->name;
grp++;
@ -1020,7 +1010,6 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pinctrl *sprd_pctl;
struct sprd_pinctrl_soc_info *pinctrl_info;
struct pinctrl_pin_desc *pin_desc;
struct resource *res;
int ret, i;
sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
@ -1028,8 +1017,7 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
if (!sprd_pctl)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sprd_pctl->base = devm_ioremap_resource(&pdev->dev, res);
sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sprd_pctl->base))
return PTR_ERR(sprd_pctl->base);

5
drivers/pinctrl/stm32/pinctrl-stm32.c
View File

@ -615,6 +615,7 @@ static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
of_node_put(np);
return ret;
}
}
@ -1468,8 +1469,10 @@ int stm32_pctl_probe(struct platform_device *pdev)
for_each_available_child_of_node(np, child) {
if (of_property_read_bool(child, "gpio-controller")) {
ret = stm32_gpiolib_register_bank(pctl, child);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
pctl->nbanks++;
}

265
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
View File

@ -1,5 +1,5 @@
/*
* Allwinner V3s SoCs pinctrl driver.
* Allwinner V3/V3s SoCs pinctrl driver.
*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*
@ -77,6 +77,30 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -98,6 +122,180 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */
/* Hole */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D4 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
SUNXI_FUNCTION(0x4, "emac")), /* RXCK */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
SUNXI_FUNCTION(0x4, "emac")), /* RXERR */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
SUNXI_FUNCTION(0x4, "emac")), /* CRS */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */
SUNXI_FUNCTION(0x4, "emac")), /* TXCK */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */
SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */
SUNXI_FUNCTION(0x4, "emac")), /* TXERR */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */
SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */
SUNXI_FUNCTION(0x4, "emac")), /* MDC */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */
SUNXI_FUNCTION(0x4, "emac")), /* MDIO */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds")), /* VPC */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* DE */
SUNXI_FUNCTION(0x3, "lvds")), /* VNC */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -291,6 +489,54 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13),
PINCTRL_SUN8I_V3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
};
static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 };
@ -305,13 +551,22 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_v3s_pinctrl_data);
unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data,
variant);
}
static const struct of_device_id sun8i_v3s_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-v3s-pinctrl", },
{}
{
.compatible = "allwinner,sun8i-v3-pinctrl",
.data = (void *)PINCTRL_SUN8I_V3
},
{
.compatible = "allwinner,sun8i-v3s-pinctrl",
.data = (void *)PINCTRL_SUN8I_V3S
},
{ },
};
static struct platform_driver sun8i_v3s_pinctrl_driver = {

2
drivers/pinctrl/sunxi/pinctrl-sunxi.h
View File

@ -94,6 +94,8 @@
#define PINCTRL_SUN4I_A10 BIT(6)
#define PINCTRL_SUN7I_A20 BIT(7)
#define PINCTRL_SUN8I_R40 BIT(8)
#define PINCTRL_SUN8I_V3 BIT(9)
#define PINCTRL_SUN8I_V3S BIT(10)
#define PIO_POW_MOD_SEL_REG 0x340

67
drivers/pinctrl/tegra/pinctrl-tegra.c
View File

@ -32,7 +32,9 @@ static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
{
writel(val, pmx->regs[bank] + reg);
writel_relaxed(val, pmx->regs[bank] + reg);
/* make sure pinmux register write completed */
pmx_readl(pmx, bank, reg);
}
static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
@ -631,6 +633,62 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
}
}
static size_t tegra_pinctrl_get_bank_size(struct device *dev,
unsigned int bank_id)
{
struct platform_device *pdev = to_platform_device(dev);
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
return resource_size(res) / 4;
}
static int tegra_pinctrl_suspend(struct device *dev)
{
struct tegra_pmx *pmx = dev_get_drvdata(dev);
u32 *backup_regs = pmx->backup_regs;
u32 *regs;
size_t bank_size;
unsigned int i, k;
for (i = 0; i < pmx->nbanks; i++) {
bank_size = tegra_pinctrl_get_bank_size(dev, i);
regs = pmx->regs[i];
for (k = 0; k < bank_size; k++)
*backup_regs++ = readl_relaxed(regs++);
}
return pinctrl_force_sleep(pmx->pctl);
}
static int tegra_pinctrl_resume(struct device *dev)
{
struct tegra_pmx *pmx = dev_get_drvdata(dev);
u32 *backup_regs = pmx->backup_regs;
u32 *regs;
size_t bank_size;
unsigned int i, k;
for (i = 0; i < pmx->nbanks; i++) {
bank_size = tegra_pinctrl_get_bank_size(dev, i);
regs = pmx->regs[i];
for (k = 0; k < bank_size; k++)
writel_relaxed(*backup_regs++, regs++);
}
/* flush all the prior writes */
readl_relaxed(pmx->regs[0]);
/* wait for pinctrl register read to complete */
rmb();
return 0;
}
const struct dev_pm_ops tegra_pinctrl_pm = {
.suspend = &tegra_pinctrl_suspend,
.resume = &tegra_pinctrl_resume
};
static bool gpio_node_has_range(const char *compatible)
{
struct device_node *np;
@ -655,6 +713,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
int i;
const char **group_pins;
int fn, gn, gfn;
unsigned long backup_regs_size = 0;
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
if (!pmx)
@ -707,6 +766,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (!res)
break;
backup_regs_size += resource_size(res);
}
pmx->nbanks = i;
@ -715,6 +775,11 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
if (!pmx->regs)
return -ENOMEM;
pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
GFP_KERNEL);
if (!pmx->backup_regs)
return -ENOMEM;
for (i = 0; i < pmx->nbanks; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);

3
drivers/pinctrl/tegra/pinctrl-tegra.h
View File

@ -17,6 +17,7 @@ struct tegra_pmx {
int nbanks;
void __iomem **regs;
u32 *backup_regs;
};
enum tegra_pinconf_param {
@ -193,6 +194,8 @@ struct tegra_pinctrl_soc_data {
bool drvtype_in_mux;
};
extern const struct dev_pm_ops tegra_pinctrl_pm;
int tegra_pinctrl_probe(struct platform_device *pdev,
const struct tegra_pinctrl_soc_data *soc_data);
#endif

1
drivers/pinctrl/tegra/pinctrl-tegra210.c
View File

@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = {
.driver = {
.name = "tegra210-pinctrl",
.of_match_table = tegra210_pinctrl_of_match,
.pm = &tegra_pinctrl_pm,
},
.probe = tegra210_pinctrl_probe,
};

10
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
View File

@ -526,8 +526,10 @@ static const unsigned uart2_pins[] = {90, 91};
static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
static const int uart3_muxvals[] = {1, 1};
static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101};
static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1};
static const unsigned uart3_ctsrts_pins[] = {96, 98};
static const int uart3_ctsrts_muxvals[] = {1, 1};
static const unsigned uart3_modem_pins[] = {97, 99, 100, 101};
static const int uart3_modem_muxvals[] = {1, 1, 1, 1};
static const unsigned usb0_pins[] = {46, 47};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
@ -600,6 +602,7 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart3_modem),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@ -636,7 +639,8 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts",
"uart3_modem"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
View File

@ -544,6 +544,8 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156};
static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
@ -574,6 +576,8 @@ static const unsigned hscin2_s_pins[] = {124, 125, 126, 127};
static const int hscin2_s_muxvals[] = {3, 3, 3, 3};
static const unsigned hscin3_s_pins[] = {129, 130, 131, 132};
static const int hscin3_s_muxvals[] = {3, 3, 3, 3};
static const unsigned hscin4_s_pins[] = {80, 81, 82, 83};
static const int hscin4_s_muxvals[] = {3, 3, 3, 3};
static const unsigned hscout0_ci_pins[] = {113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123};
static const int hscout0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
@ -619,8 +623,10 @@ static const unsigned uart2_pins[] = {90, 91};
static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {94, 95};
static const int uart3_muxvals[] = {1, 1};
static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101};
static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1};
static const unsigned uart3_ctsrts_pins[] = {96, 98};
static const int uart3_ctsrts_muxvals[] = {1, 1};
static const unsigned uart3_modem_pins[] = {97, 99, 100, 101};
static const int uart3_modem_muxvals[] = {1, 1, 1, 1};
static const unsigned usb0_pins[] = {46, 47};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {48, 49};
@ -662,6 +668,7 @@ static const unsigned int gpio_range2_pins[] = {
static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(aout1),
UNIPHIER_PINCTRL_GROUP(aout1b),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
@ -674,6 +681,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(hscin1_s),
UNIPHIER_PINCTRL_GROUP(hscin2_s),
UNIPHIER_PINCTRL_GROUP(hscin3_s),
UNIPHIER_PINCTRL_GROUP(hscin4_s),
UNIPHIER_PINCTRL_GROUP(hscout0_ci),
UNIPHIER_PINCTRL_GROUP(hscout0_p),
UNIPHIER_PINCTRL_GROUP(hscout0_s),
@ -695,6 +703,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart3_modem),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@ -704,7 +713,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
static const char * const aout1_groups[] = {"aout1"};
static const char * const aout1_groups[] = {"aout1", "aout1b"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
@ -715,6 +724,7 @@ static const char * const hscin0_groups[] = {"hscin0_ci",
static const char * const hscin1_groups[] = {"hscin1_p", "hscin1_s"};
static const char * const hscin2_groups[] = {"hscin2_s"};
static const char * const hscin3_groups[] = {"hscin3_s"};
static const char * const hscin4_groups[] = {"hscin4_s"};
static const char * const hscout0_groups[] = {"hscout0_ci",
"hscout0_p",
"hscout0_s"};
@ -734,7 +744,8 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts",
"uart3_modem"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
@ -750,6 +761,7 @@ static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
UNIPHIER_PINMUX_FUNCTION(hscin1),
UNIPHIER_PINMUX_FUNCTION(hscin2),
UNIPHIER_PINMUX_FUNCTION(hscin3),
UNIPHIER_PINMUX_FUNCTION(hscin4),
UNIPHIER_PINMUX_FUNCTION(hscout0),
UNIPHIER_PINMUX_FUNCTION(hscout1),
UNIPHIER_PINMUX_FUNCTION(i2c0),

10
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View File

@ -583,8 +583,10 @@ static const unsigned system_bus_cs3_pins[] = {156};
static const int system_bus_cs3_muxvals[] = {1};
static const unsigned uart0_pins[] = {85, 88};
static const int uart0_muxvals[] = {1, 1};
static const unsigned uart0_ctsrts_pins[] = {86, 87, 89};
static const int uart0_ctsrts_muxvals[] = {1, 1, 1};
static const unsigned uart0_ctsrts_pins[] = {86, 89};
static const int uart0_ctsrts_muxvals[] = {1, 1};
static const unsigned uart0_modem_pins[] = {87};
static const int uart0_modem_muxvals[] = {1};
static const unsigned uart1_pins[] = {155, 156};
static const int uart1_muxvals[] = {13, 13};
static const unsigned uart1b_pins[] = {69, 70};
@ -641,6 +643,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0_modem),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
UNIPHIER_PINCTRL_GROUP(uart2),
@ -667,7 +670,8 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1",
"system_bus_cs2",
"system_bus_cs3"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts",
"uart0_modem"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

10
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View File

@ -780,8 +780,10 @@ static const unsigned system_bus_cs5_pins[] = {55};
static const int system_bus_cs5_muxvals[] = {6};
static const unsigned uart0_pins[] = {135, 136};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0_ctsrts_pins[] = {137, 138, 139, 140, 141, 124};
static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned uart0_ctsrts_pins[] = {137, 139};
static const int uart0_ctsrts_muxvals[] = {3, 3};
static const unsigned uart0_modem_pins[] = {124, 138, 140, 141};
static const int uart0_modem_muxvals[] = {3, 3, 3, 3};
static const unsigned uart0b_pins[] = {11, 12};
static const int uart0b_muxvals[] = {2, 2};
static const unsigned uart1_pins[] = {115, 116};
@ -856,6 +858,7 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0_modem),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
@ -887,7 +890,8 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs3",
"system_bus_cs4",
"system_bus_cs5"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", "uart0b"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts",
"uart0_modem", "uart0b"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2", "uart2b"};
static const char * const usb0_groups[] = {"usb0"};

10
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View File

@ -1072,8 +1072,10 @@ static const unsigned uart2_pins[] = {131, 132};
static const int uart2_muxvals[] = {0, 0};
static const unsigned uart3_pins[] = {88, 89};
static const int uart3_muxvals[] = {2, 2};
static const unsigned uart3_ctsrts_pins[] = {80, 81, 82, 83, 90, 91};
static const int uart3_ctsrts_muxvals[] = {2, 2, 2, 2, 2, 2};
static const unsigned uart3_ctsrts_pins[] = {90, 91};
static const int uart3_ctsrts_muxvals[] = {2, 2};
static const unsigned uart3_modem_pins[] = {80, 81, 82, 83};
static const int uart3_modem_muxvals[] = {2, 2, 2, 2};
static const unsigned usb0_pins[] = {180, 181};
static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {182, 183};
@ -1148,6 +1150,7 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
UNIPHIER_PINCTRL_GROUP(uart3_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart3_modem),
UNIPHIER_PINCTRL_GROUP(usb0),
UNIPHIER_PINCTRL_GROUP(usb1),
UNIPHIER_PINCTRL_GROUP(usb2),
@ -1181,7 +1184,8 @@ static const char * const system_bus_groups[] = {"system_bus",
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"};
static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts",
"uart3_modem"};
static const char * const usb0_groups[] = {"usb0"};
static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};

17
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View File

@ -807,7 +807,9 @@ static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned nand_cs1_pins[] = {26, 27};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
static const unsigned pcie_pins[] = {109, 110, 111};
static const int pcie_muxvals[] = {0, 0, 0};
static const unsigned sd_pins[] = {247, 248, 249, 250, 251, 252, 253, 254, 255};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {120, 121, 122, 123};
static const int spi0_muxvals[] = {0, 0, 0, 0};
@ -839,8 +841,10 @@ static const unsigned uart0_pins[] = {47, 48};
static const int uart0_muxvals[] = {0, 0};
static const unsigned uart0b_pins[] = {227, 228};
static const int uart0b_muxvals[] = {3, 3};
static const unsigned uart0b_ctsrts_pins[] = {229, 230, 231, 232, 233, 234};
static const int uart0b_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned uart0b_ctsrts_pins[] = {232, 233};
static const int uart0b_ctsrts_muxvals[] = {3, 3};
static const unsigned uart0b_modem_pins[] = {229, 230, 231, 234};
static const int uart0b_modem_muxvals[] = {3, 3, 3, 3};
static const unsigned uart1_pins[] = {49, 50};
static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {51, 52};
@ -900,6 +904,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c5b),
UNIPHIER_PINCTRL_GROUP(i2c5c),
UNIPHIER_PINCTRL_GROUP(i2c6),
UNIPHIER_PINCTRL_GROUP(pcie),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
@ -916,6 +921,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0b_modem),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -933,6 +939,7 @@ static const char * const i2c3_groups[] = {"i2c3"};
static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const pcie_groups[] = {"pcie"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
@ -946,7 +953,8 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs5",
"system_bus_cs6",
"system_bus_cs7"};
static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
static const char * const uart0_groups[] = {"uart0", "uart0b",
"uart0b_ctsrts", "uart0b_modem"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};
@ -963,6 +971,7 @@ static const struct uniphier_pinmux_function uniphier_pro5_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c5),
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(pcie),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),

10
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View File

@ -783,8 +783,10 @@ static const unsigned uart0_pins[] = {217, 218};
static const int uart0_muxvals[] = {8, 8};
static const unsigned uart0b_pins[] = {179, 180};
static const int uart0b_muxvals[] = {10, 10};
static const unsigned uart0b_ctsrts_pins[] = {176, 177, 178, 183, 184, 185};
static const int uart0b_ctsrts_muxvals[] = {10, 10, 10, 10, 10, 10};
static const unsigned uart0b_ctsrts_pins[] = {183, 185};
static const int uart0b_ctsrts_muxvals[] = {10, 10};
static const unsigned uart0b_modem_pins[] = {176, 177, 178, 184};
static const int uart0b_modem_muxvals[] = {10, 10, 10, 10};
static const unsigned uart1_pins[] = {115, 116};
static const int uart1_muxvals[] = {8, 8};
static const unsigned uart2_pins[] = {113, 114};
@ -863,6 +865,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0b_modem),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -898,7 +901,8 @@ static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
static const char * const uart0_groups[] = {"uart0", "uart0b",
"uart0b_ctsrts", "uart0b_modem"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3", "uart3b"};

10
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
View File

@ -811,8 +811,10 @@ static const unsigned int system_bus_cs1_pins[] = {15};
static const int system_bus_cs1_muxvals[] = {0};
static const unsigned int uart0_pins[] = {92, 93};
static const int uart0_muxvals[] = {0, 0};
static const unsigned int uart0_ctsrts_pins[] = {243, 244, 245, 246, 247, 248};
static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3};
static const unsigned int uart0_ctsrts_pins[] = {243, 247};
static const int uart0_ctsrts_muxvals[] = {3, 3};
static const unsigned int uart0_modem_pins[] = {244, 245, 246, 248};
static const int uart0_modem_muxvals[] = {3, 3, 3, 3};
static const unsigned int uart1_pins[] = {94, 95};
static const int uart1_muxvals[] = {0, 0};
static const unsigned int uart2_pins[] = {96, 97};
@ -887,6 +889,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0_modem),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -914,7 +917,8 @@ static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts",
"uart0_modem"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

10
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View File

@ -513,8 +513,10 @@ static const unsigned system_bus_cs5_pins[] = {13};
static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {70, 71};
static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0_ctsrts_pins[] = {72, 73, 74};
static const int uart0_ctsrts_muxvals[] = {3, 3, 3};
static const unsigned uart0_ctsrts_pins[] = {72, 74};
static const int uart0_ctsrts_muxvals[] = {3, 3};
static const unsigned uart0_modem_pins[] = {73};
static const int uart0_modem_muxvals[] = {3};
static const unsigned uart1_pins[] = {114, 115};
static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {112, 113};
@ -572,6 +574,7 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0_ctsrts),
UNIPHIER_PINCTRL_GROUP(uart0_modem),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
UNIPHIER_PINCTRL_GROUP(uart3),
@ -599,7 +602,8 @@ static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs3",
"system_bus_cs4",
"system_bus_cs5"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts",
"uart0_modem"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
static const char * const uart3_groups[] = {"uart3"};

6
include/linux/pinctrl/consumer.h
View File

@ -24,6 +24,7 @@ struct device;
#ifdef CONFIG_PINCTRL
/* External interface to pin control */
extern bool pinctrl_gpio_can_use_line(unsigned gpio);
extern int pinctrl_gpio_request(unsigned gpio);
extern void pinctrl_gpio_free(unsigned gpio);
extern int pinctrl_gpio_direction_input(unsigned gpio);
@ -61,6 +62,11 @@ static inline int pinctrl_pm_select_idle_state(struct device *dev)
#else /* !CONFIG_PINCTRL */
static inline bool pinctrl_gpio_can_use_line(unsigned gpio)
{
return true;
}
static inline int pinctrl_gpio_request(unsigned gpio)
{
return 0;

6
include/linux/platform_data/pinctrl-single.h
View File

@ -1,4 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _PINCTRL_SINGLE_H
#define _PINCTRL_SINGLE_H
/**
* irq: optional wake-up interrupt
* rearm: optional soc specific rearm function
@ -11,3 +15,5 @@ struct pcs_pdata {
int irq;
void (*rearm)(void);
};
#endif /* _PINCTRL_SINGLE_H */