i.MX device tree changes with clock dependency:
- Add clock for i.MX6UL GPIO blocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJbUenpAAoJEFBXWFqHsHzOfQkIAIHohGhR60LspZPvYlzKgNPI m/shUfWZTqoL3ShMgIo2VWfNg0zpSnrLmhbSkdYQPVfaJfKwWniyeUya54PLYooH /wSVrF6iTskFOhbQaD4g/SckUz9wz63pymm9ze/ROnZtJvf6H2eVTDUvTQhbrIEH 02zT0E7jQhEDuJFC+yi0WrMDO/6gqxrqF6izOs52Tg//gSeBJ9RBCh7OZDXg8qXa spJM118IzvtXa/Oooq10gWFfKpDDANEWLr1calxTMU77OAygYu6NNL9CVMpw/uSj JBMx3VCZh8pAbAFqfSqYrBc6VdL3w6igHoKluVJHIhzUAzhmBSk67Lzhcwy5LzI= =6zea -----END PGP SIGNATURE----- Merge tag 'imx-dt-clkdep-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt i.MX device tree changes with clock dependency: - Add clock for i.MX6UL GPIO blocks * tag 'imx-dt-clkdep-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx6ul: add GPIO clocks clk: imx6ul: remove clks_init_on array clk: imx6ul: add GPIO clock gates dt-bindings: clock: imx6ul: Do not change the clock definition order Signed-off-by: Olof Johansson <olof@lixom.net>hifive-unleashed-5.1
Olof Johansson
commit
3c34a84544
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@ -433,6 +433,7 @@
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reg = <0x0209c000 0x4000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -446,6 +447,7 @@
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reg = <0x020a0000 0x4000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -458,6 +460,7 @@
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reg = <0x020a4000 0x4000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -470,6 +473,7 @@
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reg = <0x020a8000 0x4000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_GPIO4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -482,6 +486,7 @@
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reg = <0x020ac000 0x4000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_GPIO5>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -79,12 +79,6 @@ static const char *cko_sels[] = { "cko1", "cko2", };
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static struct clk *clks[IMX6UL_CLK_END];
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static struct clk_onecell_data clk_data;
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static int const clks_init_on[] __initconst = {
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IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,
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IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
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IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
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};
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static const struct clk_div_table clk_enet_ref_table[] = {
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{ .val = 0, .div = 20, },
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{ .val = 1, .div = 10, },
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@ -129,7 +123,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@ -336,8 +329,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
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/* CCGR0 */
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clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
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clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
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clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
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clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
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clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4);
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clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
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clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
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@ -360,6 +353,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
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if (clk_on_imx6ull())
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clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
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clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
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/* CCGR1 */
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clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
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@ -376,6 +370,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
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clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
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clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
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clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
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clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
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/* CCGR2 */
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if (clk_on_imx6ull()) {
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@ -389,6 +385,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
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clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
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clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14);
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clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
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clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
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clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
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@ -405,11 +402,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6);
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clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6);
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clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
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clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
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clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
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clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
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clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
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clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
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clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28);
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clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
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clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
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clks[IMX6UL_CLK_AXI] = imx_clk_gate_flags("axi", "axi_podf", base + 0x74, 28, CLK_IS_CRITICAL);
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/* CCGR4 */
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clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12);
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@ -423,7 +421,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30);
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/* CCGR5 */
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clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
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clks[IMX6UL_CLK_ROM] = imx_clk_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
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clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
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clks[IMX6UL_CLK_KPP] = imx_clk_gate2("kpp", "ipg", base + 0x7c, 8);
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clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10);
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@ -497,10 +495,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
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clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
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/* keep all the clks on just for bringup */
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for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
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clk_prepare_enable(clks[clks_init_on[i]]);
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if (clk_on_imx6ull())
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clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]);
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@ -235,27 +235,31 @@
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#define IMX6UL_CLK_CSI_PODF 222
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#define IMX6UL_CLK_PLL3_120M 223
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#define IMX6UL_CLK_KPP 224
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#define IMX6UL_CLK_CKO1_SEL 225
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#define IMX6UL_CLK_CKO1_PODF 226
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#define IMX6UL_CLK_CKO1 227
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#define IMX6UL_CLK_CKO2_SEL 228
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#define IMX6UL_CLK_CKO2_PODF 229
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#define IMX6UL_CLK_CKO2 230
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#define IMX6UL_CLK_CKO 231
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#define IMX6ULL_CLK_ESAI_PRED 225
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#define IMX6ULL_CLK_ESAI_PODF 226
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#define IMX6ULL_CLK_ESAI_EXTAL 227
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#define IMX6ULL_CLK_ESAI_MEM 228
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#define IMX6ULL_CLK_ESAI_IPG 229
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#define IMX6ULL_CLK_DCP_CLK 230
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#define IMX6ULL_CLK_EPDC_PRE_SEL 231
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#define IMX6ULL_CLK_EPDC_SEL 232
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#define IMX6ULL_CLK_EPDC_PODF 233
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#define IMX6ULL_CLK_EPDC_ACLK 234
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#define IMX6ULL_CLK_EPDC_PIX 235
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#define IMX6ULL_CLK_ESAI_SEL 236
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#define IMX6UL_CLK_CKO1_SEL 237
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#define IMX6UL_CLK_CKO1_PODF 238
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#define IMX6UL_CLK_CKO1 239
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#define IMX6UL_CLK_CKO2_SEL 240
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#define IMX6UL_CLK_CKO2_PODF 241
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#define IMX6UL_CLK_CKO2 242
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#define IMX6UL_CLK_CKO 243
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#define IMX6UL_CLK_GPIO1 244
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#define IMX6UL_CLK_GPIO2 245
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#define IMX6UL_CLK_GPIO3 246
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#define IMX6UL_CLK_GPIO4 247
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#define IMX6UL_CLK_GPIO5 248
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/* For i.MX6ULL */
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#define IMX6ULL_CLK_ESAI_PRED 232
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#define IMX6ULL_CLK_ESAI_PODF 233
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#define IMX6ULL_CLK_ESAI_EXTAL 234
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#define IMX6ULL_CLK_ESAI_MEM 235
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#define IMX6ULL_CLK_ESAI_IPG 236
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#define IMX6ULL_CLK_DCP_CLK 237
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#define IMX6ULL_CLK_EPDC_PRE_SEL 238
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#define IMX6ULL_CLK_EPDC_SEL 239
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#define IMX6ULL_CLK_EPDC_PODF 240
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#define IMX6ULL_CLK_EPDC_ACLK 241
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#define IMX6ULL_CLK_EPDC_PIX 242
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#define IMX6ULL_CLK_ESAI_SEL 243
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#define IMX6UL_CLK_END 244
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#define IMX6UL_CLK_END 249
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#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
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