drm/i915: BDW needs D_COMP writes through MCHBAR
That's what the spec said! And HSW needs it through pcode (you can only read it through MCHBAR), so create hsw_write_dcomp to abstract the weirdness. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -6885,6 +6885,22 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
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{
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struct drm_device *dev = dev_priv->dev;
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if (IS_HASWELL(dev)) {
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mutex_lock(&dev_priv->rps.hw_lock);
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if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
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val))
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DRM_ERROR("Failed to disable D_COMP\n");
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mutex_unlock(&dev_priv->rps.hw_lock);
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} else {
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I915_WRITE(D_COMP, val);
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}
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POSTING_READ(D_COMP);
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}
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/*
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* This function implements pieces of two sequences from BSpec:
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* - Sequence for display software to disable LCPLL
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@ -6922,11 +6938,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
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val = I915_READ(D_COMP);
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val |= D_COMP_COMP_DISABLE;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
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DRM_ERROR("Failed to disable D_COMP\n");
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mutex_unlock(&dev_priv->rps.hw_lock);
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POSTING_READ(D_COMP);
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hsw_write_dcomp(dev_priv, val);
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ndelay(100);
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if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
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@ -6981,11 +6993,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
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val = I915_READ(D_COMP);
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val |= D_COMP_COMP_FORCE;
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val &= ~D_COMP_COMP_DISABLE;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
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DRM_ERROR("Failed to enable D_COMP\n");
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mutex_unlock(&dev_priv->rps.hw_lock);
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POSTING_READ(D_COMP);
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hsw_write_dcomp(dev_priv, val);
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val = I915_READ(LCPLL_CTL);
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val &= ~LCPLL_PLL_DISABLE;
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