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iio: trigger: stm32-timer: disable master mode when stopping 

commit 29e8c8253d upstream.

Master mode should be disabled when stopping. This mainly impacts
possible other use-case after timer has been stopped. Currently,
master mode remains set (from start routine).

Fixes: 6fb34812c2 ("iio: stm32 trigger: Add support for TRGO2 triggers")

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5.4-rM2-2.2.x-imx-squashed
Fabrice Gasnier 2020-02-14 17:46:35 +01:00 committed by Greg Kroah-Hartman
parent eb5f46b0cc
commit 3c69b794f9
1 changed files with 9 additions and 2 deletions
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11
drivers/iio/trigger/stm32-timer-trigger.c
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@ -161,7 +161,8 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,
return 0; return 0;
} }
static void stm32_timer_stop(struct stm32_timer_trigger *priv) static void stm32_timer_stop(struct stm32_timer_trigger *priv,
struct iio_trigger *trig)
{ {
u32 ccer, cr1; u32 ccer, cr1;
@ -179,6 +180,12 @@ static void stm32_timer_stop(struct stm32_timer_trigger *priv)
regmap_write(priv->regmap, TIM_PSC, 0); regmap_write(priv->regmap, TIM_PSC, 0);
regmap_write(priv->regmap, TIM_ARR, 0); regmap_write(priv->regmap, TIM_ARR, 0);
/* Force disable master mode */
if (stm32_timer_is_trgo2_name(trig->name))
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
else
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
/* Make sure that registers are updated */ /* Make sure that registers are updated */
regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
} }
@ -197,7 +204,7 @@ static ssize_t stm32_tt_store_frequency(struct device *dev,
return ret; return ret;
if (freq == 0) { if (freq == 0) {
stm32_timer_stop(priv); stm32_timer_stop(priv, trig);
} else { } else {
ret = stm32_timer_start(priv, trig, freq); ret = stm32_timer_start(priv, trig, freq);
if (ret) if (ret)