MIPS: Refactor dumping of TLB registers for r3k/r4k
The TLB registers are dumped in a couble of places:
- sysrq_tlbdump_single() - when dumping TLB state.
- do_mcheck() - in response to a machine check error.
The main TLB registers also differ between r3k and r4k, but r4k appears
to be assumed.
Refactor this code into a dump_tlb_regs() function, implemented for both
r3k and r4k, and used by both of the above functions.
Fixes: d1e9a4f547
("MIPS: Add SysRq operation to dump TLBs on all CPUs")
Suggested-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10721/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
parent
0f6ce77538
commit
3c865dd9c1
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@ -11,6 +11,7 @@
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/*
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/*
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* TLB debugging functions:
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* TLB debugging functions:
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*/
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*/
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extern void dump_tlb_regs(void);
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extern void dump_tlb_all(void);
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extern void dump_tlb_all(void);
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#endif /* __ASM_TLBDEBUG_H */
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#endif /* __ASM_TLBDEBUG_H */
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@ -21,24 +21,12 @@ static DEFINE_SPINLOCK(show_lock);
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static void sysrq_tlbdump_single(void *dummy)
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static void sysrq_tlbdump_single(void *dummy)
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{
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned long flags;
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unsigned long flags;
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spin_lock_irqsave(&show_lock, flags);
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spin_lock_irqsave(&show_lock, flags);
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pr_info("CPU%d:\n", smp_processor_id());
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pr_info("CPU%d:\n", smp_processor_id());
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pr_info("Index : %0x\n", read_c0_index());
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dump_tlb_regs();
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pr_info("Pagemask: %0x\n", read_c0_pagemask());
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pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
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pr_info("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
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pr_info("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
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pr_info("Wired : %0x\n", read_c0_wired());
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pr_info("Pagegrain: %0x\n", read_c0_pagegrain());
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if (cpu_has_htw) {
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pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
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pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());
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pr_info("PWCtl : %0x\n", read_c0_pwctl());
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}
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pr_info("\n");
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pr_info("\n");
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dump_tlb_all();
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dump_tlb_all();
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pr_info("\n");
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pr_info("\n");
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@ -1523,7 +1523,6 @@ asmlinkage void do_watch(struct pt_regs *regs)
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asmlinkage void do_mcheck(struct pt_regs *regs)
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asmlinkage void do_mcheck(struct pt_regs *regs)
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{
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{
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const int field = 2 * sizeof(unsigned long);
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int multi_match = regs->cp0_status & ST0_TS;
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int multi_match = regs->cp0_status & ST0_TS;
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enum ctx_state prev_state;
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enum ctx_state prev_state;
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mm_segment_t old_fs = get_fs();
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mm_segment_t old_fs = get_fs();
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@ -1532,19 +1531,8 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
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show_regs(regs);
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show_regs(regs);
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if (multi_match) {
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if (multi_match) {
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pr_err("Index : %0x\n", read_c0_index());
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dump_tlb_regs();
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pr_err("Pagemask: %0x\n", read_c0_pagemask());
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pr_info("\n");
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pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
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pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
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pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
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pr_err("Wired : %0x\n", read_c0_wired());
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pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
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if (cpu_has_htw) {
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pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
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pr_err("PWSize : %0*lx\n", field, read_c0_pwsize());
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pr_err("PWCtl : %0x\n", read_c0_pwctl());
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}
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pr_err("\n");
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dump_tlb_all();
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dump_tlb_all();
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}
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}
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@ -13,6 +13,24 @@
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#include <asm/pgtable.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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#include <asm/tlbdebug.h>
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void dump_tlb_regs(void)
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{
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const int field = 2 * sizeof(unsigned long);
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pr_info("Index : %0x\n", read_c0_index());
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pr_info("PageMask : %0x\n", read_c0_pagemask());
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pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
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pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
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pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
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pr_info("Wired : %0x\n", read_c0_wired());
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pr_info("PageGrain: %0x\n", read_c0_pagegrain());
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if (cpu_has_htw) {
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pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
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pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());
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pr_info("PWCtl : %0x\n", read_c0_pwctl());
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}
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}
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static inline const char *msk2str(unsigned int mask)
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static inline const char *msk2str(unsigned int mask)
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{
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{
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switch (mask) {
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switch (mask) {
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@ -14,6 +14,17 @@
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#include <asm/pgtable.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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#include <asm/tlbdebug.h>
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extern int r3k_have_wired_reg;
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void dump_tlb_regs(void)
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{
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pr_info("Index : %0x\n", read_c0_index());
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pr_info("EntryHi : %0lx\n", read_c0_entryhi());
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pr_info("EntryLo : %0lx\n", read_c0_entrylo0());
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if (r3k_have_wired_reg)
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pr_info("Wired : %0x\n", read_c0_wired());
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}
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static void dump_tlb(int first, int last)
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static void dump_tlb(int first, int last)
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{
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{
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int i;
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int i;
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@ -36,7 +36,7 @@ extern void build_tlb_refill_handler(void);
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"nop\n\t" \
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"nop\n\t" \
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".set pop\n\t")
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".set pop\n\t")
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static int r3k_have_wired_reg; /* Should be in cpu_data? */
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int r3k_have_wired_reg; /* Should be in cpu_data? */
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/* TLB operations. */
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/* TLB operations. */
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static void local_flush_tlb_from(int entry)
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static void local_flush_tlb_from(int entry)
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