drm/armada: update planes after the dumb frame is complete
Write out the plane updates after the dumb frame has completed, but just before the blank period. This allows all the plane updates to be performed in a flicker-free non-tearing manner. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -197,21 +197,27 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
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writel_relaxed(val, base + LCD_SPU_ADV_REG);
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}
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if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
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writel_relaxed(dcrtc->cursor_hw_pos,
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base + LCD_SPU_HWC_OVSA_HPXL_VLN);
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writel_relaxed(dcrtc->cursor_hw_sz,
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base + LCD_SPU_HWC_HPXL_VLN);
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armada_updatel(CFG_HWC_ENA,
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CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
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base + LCD_SPU_DMA_CTRL0);
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dcrtc->cursor_update = false;
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if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) {
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if (dcrtc->update_pending) {
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armada_drm_crtc_update_regs(dcrtc, dcrtc->regs);
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dcrtc->update_pending = false;
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}
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if (dcrtc->cursor_update) {
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writel_relaxed(dcrtc->cursor_hw_pos,
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base + LCD_SPU_HWC_OVSA_HPXL_VLN);
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writel_relaxed(dcrtc->cursor_hw_sz,
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base + LCD_SPU_HWC_HPXL_VLN);
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armada_updatel(CFG_HWC_ENA,
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CFG_HWC_ENA | CFG_HWC_1BITMOD |
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CFG_HWC_1BITENA,
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base + LCD_SPU_DMA_CTRL0);
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dcrtc->cursor_update = false;
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}
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armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
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}
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spin_unlock(&dcrtc->irq_lock);
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if (stat & VSYNC_IRQ) {
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if (stat & VSYNC_IRQ && !dcrtc->update_pending) {
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event = xchg(&dcrtc->event, NULL);
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if (event) {
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spin_lock(&dcrtc->crtc.dev->event_lock);
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@ -360,22 +366,26 @@ static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_crtc_state)
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{
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struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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unsigned long flags;
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DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
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armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx);
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spin_lock_irqsave(&dcrtc->irq_lock, flags);
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armada_drm_crtc_update_regs(dcrtc, dcrtc->regs);
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spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
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/*
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* If we aren't doing a full modeset, then we need to queue
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* the event here.
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*/
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if (!drm_atomic_crtc_needs_modeset(crtc->state))
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if (!drm_atomic_crtc_needs_modeset(crtc->state)) {
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dcrtc->update_pending = true;
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armada_drm_crtc_queue_state_event(crtc);
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spin_lock_irq(&dcrtc->irq_lock);
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armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
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spin_unlock_irq(&dcrtc->irq_lock);
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} else {
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spin_lock_irq(&dcrtc->irq_lock);
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armada_drm_crtc_update_regs(dcrtc, dcrtc->regs);
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spin_unlock_irq(&dcrtc->irq_lock);
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}
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}
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static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc,
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@ -532,7 +542,6 @@ static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
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if (!dcrtc->cursor_obj || !h || !w) {
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spin_lock_irq(&dcrtc->irq_lock);
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armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
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dcrtc->cursor_update = false;
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armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
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spin_unlock_irq(&dcrtc->irq_lock);
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@ -556,7 +565,6 @@ static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
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if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
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spin_lock_irq(&dcrtc->irq_lock);
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armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
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dcrtc->cursor_update = false;
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armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
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spin_unlock_irq(&dcrtc->irq_lock);
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@ -70,6 +70,7 @@ struct armada_crtc {
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spinlock_t irq_lock;
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uint32_t irq_ena;
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bool update_pending;
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struct drm_pending_vblank_event *event;
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struct armada_regs atomic_regs[32];
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struct armada_regs *regs;
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