drm/nva3/clk: Set intermediate core clock on reclocking
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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a749a1fb55
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3d40a7176d
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@ -29,6 +29,7 @@ enum nv_clk_src {
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nv_clk_src_mdiv,
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nv_clk_src_core,
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nv_clk_src_core_intm,
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nv_clk_src_shader,
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nv_clk_src_mem,
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@ -142,6 +142,7 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
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case nv_clk_src_crystal:
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return nv_device(priv)->crystal;
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case nv_clk_src_core:
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case nv_clk_src_core_intm:
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return read_pll(priv, 0x00, 0x4200);
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case nv_clk_src_shader:
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return read_pll(priv, 0x01, 0x4220);
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@ -226,7 +227,6 @@ nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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{
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struct nouveau_bios *bios = nouveau_bios(clock);
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struct nva3_clock_priv *priv = (void *)clock;
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int clk_khz;
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struct nvbios_pll limits;
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int P, N, M, diff;
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int ret;
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@ -235,10 +235,10 @@ nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
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* PLL and use the divider instead. */
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clk_khz = nva3_clk_info(clock, clk, khz, info);
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diff = khz - clk_khz;
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ret = nva3_clk_info(clock, clk, khz, info);
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diff = khz - ret;
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if (!pll || (diff >= -2000 && diff < 3000)) {
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return clk_khz;
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goto out;
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}
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/* Try with PLL */
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@ -246,8 +246,8 @@ nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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if (ret)
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return ret;
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clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
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if (clk_khz != limits.refclk)
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ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
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if (ret != limits.refclk)
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return -EINVAL;
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ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
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@ -255,6 +255,9 @@ nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
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info->pll = (P << 16) | (N << 8) | M;
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}
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out:
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info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
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return ret ? ret : -ERANGE;
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}
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@ -371,10 +374,26 @@ prog_host(struct nva3_clock_priv *priv)
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nv_wr32(priv, 0xc044, 0x3e);
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}
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static void
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prog_core(struct nva3_clock_priv *priv, int idx)
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{
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struct nva3_clock_info *info = &priv->eng[idx];
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u32 fb_delay = nv_rd32(priv, 0x10002c);
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if (fb_delay < info->fb_delay)
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nv_wr32(priv, 0x10002c, info->fb_delay);
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prog_pll(priv, 0x00, 0x004200, idx);
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if (fb_delay > info->fb_delay)
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nv_wr32(priv, 0x10002c, info->fb_delay);
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}
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static int
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nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
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{
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struct nva3_clock_priv *priv = (void *)clk;
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struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
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int ret;
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if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
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@ -384,6 +403,16 @@ nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
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(ret = calc_host(priv, cstate)))
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return ret;
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/* XXX: Should be reading the highest bit in the VBIOS clock to decide
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* whether to use a PLL or not... but using a PLL defeats the purpose */
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if (core->pll) {
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ret = nva3_clk_info(clk, 0x10,
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cstate->domain[nv_clk_src_core_intm],
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&priv->eng[nv_clk_src_core_intm]);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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@ -391,7 +420,12 @@ static int
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nva3_clock_prog(struct nouveau_clock *clk)
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{
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struct nva3_clock_priv *priv = (void *)clk;
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prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
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struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
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if (core->pll)
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prog_core(priv, nv_clk_src_core_intm);
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prog_core(priv, nv_clk_src_core);
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prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
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prog_clk(priv, 0x20, nv_clk_src_disp);
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prog_clk(priv, 0x21, nv_clk_src_vdec);
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@ -406,13 +440,14 @@ nva3_clock_tidy(struct nouveau_clock *clk)
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static struct nouveau_clocks
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nva3_domain[] = {
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{ nv_clk_src_crystal, 0xff },
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{ nv_clk_src_core , 0x00, 0, "core", 1000 },
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{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
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{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
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{ nv_clk_src_vdec , 0x03 },
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{ nv_clk_src_disp , 0x04 },
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{ nv_clk_src_host , 0x05 },
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{ nv_clk_src_crystal , 0xff },
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{ nv_clk_src_core , 0x00, 0, "core", 1000 },
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{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
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{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
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{ nv_clk_src_vdec , 0x03 },
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{ nv_clk_src_disp , 0x04 },
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{ nv_clk_src_host , 0x05 },
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{ nv_clk_src_core_intm, 0x06 },
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{ nv_clk_src_max }
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};
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@ -10,6 +10,7 @@ struct nva3_clock_info {
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NVA3_HOST_277,
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NVA3_HOST_CLK,
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} host_out;
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u32 fb_delay;
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};
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int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
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