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arm: dts: rockchip: add reset node for the exist saradc SoCs 

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
hifive-unleashed-5.1
Caesar Wang 2016-07-27 22:24:07 +08:00 committed by Jonathan Cameron
parent 78ec79bfd5
commit 3d4267a5a3
3 changed files with 6 additions and 0 deletions
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2
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -197,6 +197,8 @@
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};

2
arch/arm/boot/dts/rk3288.dtsi
View File

@ -279,6 +279,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};

2
arch/arm/boot/dts/rk3xxx.dtsi
View File

@ -399,6 +399,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};