drm/amd/amdgpu: Various cleanups for DCEv6
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1505,10 +1505,7 @@ static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
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u32 vga_control;
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vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
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if (enable)
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WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
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else
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WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
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WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
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}
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static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
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@ -1517,10 +1514,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
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struct drm_device *dev = crtc->dev;
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struct amdgpu_device *adev = dev->dev_private;
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if (enable)
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WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
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else
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WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
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WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
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}
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static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
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@ -1550,8 +1544,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
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if (atomic) {
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amdgpu_fb = to_amdgpu_framebuffer(fb);
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target_fb = fb;
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}
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else {
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} else {
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amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
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target_fb = crtc->primary->fb;
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}
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@ -1565,9 +1558,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
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if (unlikely(r != 0))
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return r;
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if (atomic)
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if (atomic) {
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fb_location = amdgpu_bo_gpu_offset(abo);
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else {
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} else {
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r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
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if (unlikely(r != 0)) {
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amdgpu_bo_unreserve(abo);
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@ -1663,8 +1656,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
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fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
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fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
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fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
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} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
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} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
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fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
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}
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pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
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fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
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@ -1828,26 +1822,13 @@ static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
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switch (amdgpu_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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if (dig->linkb)
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return 1;
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else
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return 0;
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break;
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return dig->linkb ? 1 : 0;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
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if (dig->linkb)
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return 3;
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else
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return 2;
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break;
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return dig->linkb ? 3 : 2;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
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if (dig->linkb)
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return 5;
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else
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return 4;
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break;
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return dig->linkb ? 5 : 4;
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
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return 6;
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break;
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default:
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DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
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return 0;
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@ -2082,7 +2063,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
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amdgpu_crtc->cursor_y);
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dce_v6_0_show_cursor(crtc);
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dce_v6_0_lock_cursor(crtc, false);
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}
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}
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@ -2405,15 +2385,11 @@ static int dce_v6_0_sw_init(void *handle)
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adev->mode_info.mode_config_initialized = true;
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adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
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adev->ddev->mode_config.async_page_flip = true;
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adev->ddev->mode_config.max_width = 16384;
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adev->ddev->mode_config.max_height = 16384;
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adev->ddev->mode_config.preferred_depth = 24;
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adev->ddev->mode_config.prefer_shadow = 1;
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adev->ddev->mode_config.fb_base = adev->mc.aper_base;
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r = amdgpu_modeset_create_props(adev);
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@ -2459,7 +2435,6 @@ static int dce_v6_0_sw_fini(void *handle)
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drm_kms_helper_poll_fini(adev->ddev);
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dce_v6_0_audio_fini(adev);
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dce_v6_0_afmt_fini(adev);
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drm_mode_config_cleanup(adev->ddev);
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@ -3087,7 +3062,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
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}
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amdgpu_encoder->enc_priv = NULL;
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amdgpu_encoder->encoder_enum = encoder_enum;
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amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
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amdgpu_encoder->devices = supported_device;
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