drm/nva3/clk: Parse clock control registers more accurately
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -20,6 +20,7 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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* Roy Spliet
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*/
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#include <subdev/bios.h>
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@ -42,9 +43,17 @@ static u32
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read_vco(struct nva3_clock_priv *priv, int clk)
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{
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u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
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if ((sctl & 0x00000030) != 0x00000030)
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switch (sctl & 0x00000030) {
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case 0x00000000:
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return nv_device(priv)->crystal;
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case 0x00000020:
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return read_pll(priv, 0x41, 0x00e820);
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return read_pll(priv, 0x42, 0x00e8a0);
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case 0x00000030:
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return read_pll(priv, 0x42, 0x00e8a0);
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default:
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return 0;
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}
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}
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static u32
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@ -66,14 +75,25 @@ read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
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if (!ignore_en && !(sctl & 0x00000100))
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return 0;
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/* out_alt */
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if (sctl & 0x00000400)
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return 108000;
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/* vco_out */
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switch (sctl & 0x00003000) {
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case 0x00000000:
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return nv_device(priv)->crystal;
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if (!(sctl & 0x00000200))
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return nv_device(priv)->crystal;
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return 0;
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case 0x00002000:
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if (sctl & 0x00000040)
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return 108000;
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return 100000;
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case 0x00003000:
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/* vco_enable */
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if (!(sctl & 0x00000001))
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return 0;
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sclk = read_vco(priv, clk);
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sdiv = ((sctl & 0x003f0000) >> 16) + 2;
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return (sclk * 2) / sdiv;
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@ -95,7 +115,9 @@ read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
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N = (coef & 0x0000ff00) >> 8;
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P = (coef & 0x003f0000) >> 16;
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/* no post-divider on these.. */
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/* no post-divider on these..
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* XXX: it looks more like two post-"dividers" that
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* cross each other out in the default RPLL config */
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if ((pll & 0x00ff00) == 0x00e800)
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P = 1;
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@ -136,6 +158,8 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
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nv_error(clk, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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return 0;
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}
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int
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