Blackfin: clean up style in irq defines
These files had a lot of whitespace damage, mostly due to copying and pasting original files that had damage. The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so punt them all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>hifive-unleashed-5.1
Mike Frysinger
parent
6adc521e71
commit
3dd666067d
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@ -202,4 +202,4 @@
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#define IRQ_PWM_SYNC_POS 24
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#define IRQ_PTP_STAT_POS 28
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#endif /* _BF518_IRQ_H_ */
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#endif
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@ -201,4 +201,4 @@
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#define IRQ_USB_INT2_POS 24
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#define IRQ_USB_DMA_POS 28
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#endif /* _BF527_IRQ_H_ */
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#endif
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@ -9,33 +9,34 @@
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#include <mach-common/irq.h>
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#define SYS_IRQS 31
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#define NR_PERI_INTS 24
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#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
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#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
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#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
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#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
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#define IRQ_RTC 14 /*RTC Interrupt */
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#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
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#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
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#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
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#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
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#define IRQ_TIMER0 23 /*Timer 0 */
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#define IRQ_TIMER1 24 /*Timer 1 */
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#define IRQ_TIMER2 25 /*Timer 2 */
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#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
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#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
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#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
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#define IRQ_WATCH 30 /*Watch Dog Timer */
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#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
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#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
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#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
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#define IRQ_UART0_ERROR 13 /* UART Error Interrupt */
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#define IRQ_RTC 14 /* RTC Interrupt */
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#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 16 /* DMA1 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 17 /* DMA2 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 18 /* DMA3 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 19 /* DMA4 Interrupt (SPORT1 TX) */
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#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
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#define IRQ_UART0_RX 21 /* DMA6 Interrupt (UART RX) */
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#define IRQ_UART0_TX 22 /* DMA7 Interrupt (UART TX) */
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#define IRQ_TIMER0 23 /* Timer 0 */
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#define IRQ_TIMER1 24 /* Timer 1 */
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#define IRQ_TIMER2 25 /* Timer 2 */
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#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
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#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
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#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
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#define IRQ_WATCH 30 /* Watch Dog Timer */
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#define SYS_IRQS 31
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#define IRQ_PF0 33
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#define IRQ_PF1 34
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@ -58,7 +59,7 @@
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#define NR_MACH_IRQS (IRQ_PF15 + 1)
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/* IAR0 BIT FIELDS*/
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/* IAR0 BIT FIELDS */
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#define RTC_ERROR_POS 28
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#define UART_ERROR_POS 24
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#define SPORT1_ERROR_POS 20
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@ -68,7 +69,7 @@
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#define DMA_ERROR_POS 4
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#define PLLWAKE_ERROR_POS 0
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/* IAR1 BIT FIELDS*/
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/* IAR1 BIT FIELDS */
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#define DMA7_UARTTX_POS 28
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#define DMA6_UARTRX_POS 24
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#define DMA5_SPI_POS 20
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@ -78,7 +79,7 @@
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#define DMA1_SPORT0RX_POS 4
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#define DMA0_PPI_POS 0
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/* IAR2 BIT FIELDS*/
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/* IAR2 BIT FIELDS */
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#define WDTIMER_POS 28
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#define MEMDMA1_POS 24
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#define MEMDMA0_POS 20
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@ -88,4 +89,4 @@
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#define TIMER1_POS 4
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#define TIMER0_POS 0
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#endif /* _BF533_IRQ_H_ */
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#endif
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@ -9,51 +9,52 @@
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#include <mach-common/irq.h>
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#define SYS_IRQS 39
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#define NR_PERI_INTS 32
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#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
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#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
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#define IRQ_RTC 10 /*RTC Interrupt */
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#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
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#define IRQ_TWI 16 /*TWI Interrupt */
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#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
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#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
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#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
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#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
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#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
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#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
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#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
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#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
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#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
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#define IRQ_TIMER0 26 /*Timer 0 */
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#define IRQ_TIMER1 27 /*Timer 1 */
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#define IRQ_TIMER2 28 /*Timer 2 */
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#define IRQ_TIMER3 29 /*Timer 3 */
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#define IRQ_TIMER4 30 /*Timer 4 */
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#define IRQ_TIMER5 31 /*Timer 5 */
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#define IRQ_TIMER6 32 /*Timer 6 */
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#define IRQ_TIMER7 33 /*Timer 7 */
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#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
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#define IRQ_GENERIC_ERROR 9 /* GENERIC Error Interrupt */
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#define IRQ_RTC 10 /* RTC Interrupt */
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#define IRQ_PPI 11 /* DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 12 /* DMA3 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 13 /* DMA4 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 14 /* DMA5 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 15 /* DMA6 Interrupt (SPORT1 TX) */
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#define IRQ_TWI 16 /* TWI Interrupt */
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#define IRQ_SPI 17 /* DMA7 Interrupt (SPI) */
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#define IRQ_UART0_RX 18 /* DMA8 Interrupt (UART0 RX) */
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#define IRQ_UART0_TX 19 /* DMA9 Interrupt (UART0 TX) */
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#define IRQ_UART1_RX 20 /* DMA10 Interrupt (UART1 RX) */
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#define IRQ_UART1_TX 21 /* DMA11 Interrupt (UART1 TX) */
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#define IRQ_CAN_RX 22 /* CAN Receive Interrupt */
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#define IRQ_CAN_TX 23 /* CAN Transmit Interrupt */
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#define IRQ_MAC_RX 24 /* DMA1 (Ethernet RX) Interrupt */
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#define IRQ_MAC_TX 25 /* DMA2 (Ethernet TX) Interrupt */
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#define IRQ_TIMER0 26 /* Timer 0 */
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#define IRQ_TIMER1 27 /* Timer 1 */
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#define IRQ_TIMER2 28 /* Timer 2 */
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#define IRQ_TIMER3 29 /* Timer 3 */
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#define IRQ_TIMER4 30 /* Timer 4 */
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#define IRQ_TIMER5 31 /* Timer 5 */
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#define IRQ_TIMER6 32 /* Timer 6 */
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#define IRQ_TIMER7 33 /* Timer 7 */
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#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
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#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
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#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
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#define IRQ_MEM_DMA0 36 /* (Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 37 /* (Memory DMA Stream 1) */
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#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
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#define IRQ_WATCH 38 /*Watch Dog Timer */
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#define IRQ_WATCH 38 /* Watch Dog Timer */
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#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
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#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
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#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
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#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
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#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
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#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
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#define SYS_IRQS 39
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#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
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#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
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#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
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#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
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#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
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#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
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#define IRQ_PF0 50
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#define IRQ_PF1 51
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@ -119,7 +120,7 @@
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#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
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/* IAR0 BIT FIELDS*/
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/* IAR0 BIT FIELDS */
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA_ERROR_POS 4
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#define IRQ_ERROR_POS 8
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@ -129,7 +130,7 @@
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#define IRQ_SPORT0_TX_POS 24
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#define IRQ_SPORT1_RX_POS 28
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/* IAR1 BIT FIELDS*/
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/* IAR1 BIT FIELDS */
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#define IRQ_SPORT1_TX_POS 0
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#define IRQ_TWI_POS 4
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#define IRQ_SPI_POS 8
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@ -139,7 +140,7 @@
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#define IRQ_UART1_TX_POS 24
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#define IRQ_CAN_RX_POS 28
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/* IAR2 BIT FIELDS*/
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/* IAR2 BIT FIELDS */
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#define IRQ_CAN_TX_POS 0
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#define IRQ_MAC_RX_POS 4
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#define IRQ_MAC_TX_POS 8
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@ -149,7 +150,7 @@
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#define IRQ_TIMER3_POS 24
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#define IRQ_TIMER4_POS 28
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/* IAR3 BIT FIELDS*/
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/* IAR3 BIT FIELDS */
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#define IRQ_TIMER5_POS 0
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#define IRQ_TIMER6_POS 4
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#define IRQ_TIMER7_POS 8
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@ -159,4 +160,4 @@
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#define IRQ_MEM_DMA1_POS 24
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#define IRQ_WATCH_POS 28
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#endif /* _BF537_IRQ_H_ */
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#endif
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@ -144,4 +144,5 @@
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#define IRQ_CAN_TX_POS 0
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#define IRQ_MEM1_DMA0_POS 4
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#define IRQ_MEM1_DMA1_POS 8
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#endif /* _BF538_IRQ_H_ */
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#endif
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@ -9,7 +9,7 @@
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#include <mach-common/irq.h>
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#define NR_PERI_INTS (32 * 3)
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#define NR_PERI_INTS (3 * 32)
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#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
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#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
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@ -451,4 +451,4 @@ struct bfin_pint_regs {
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#endif
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#endif /* _BF548_IRQ_H_ */
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#endif
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@ -9,11 +9,9 @@
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#include <mach-common/irq.h>
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#define SYS_IRQS 71
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#define NR_PERI_INTS 64
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#define NR_PERI_INTS (2 * 32)
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#define IVG_BASE 7
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/* IVG 7 */
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#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
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#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
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#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
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#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
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#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
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#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
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/* IVG 8 */
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#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed */
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#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
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#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
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#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
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#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
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#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
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#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
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/* IVG 9 */
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#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
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#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
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#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
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#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
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#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
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#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
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/* IVG 10 */
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#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
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#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
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#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
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#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
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#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
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#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
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/* IVG 11 */
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#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
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#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
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#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
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#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
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#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
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#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
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/* IVG 8 */
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#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
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#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
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#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
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#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
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#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
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#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
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/* IVG 9 */
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#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
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#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
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#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
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#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
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/* IVG 12 */
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#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
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#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
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#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
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#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
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/* IVG 13 */
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#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
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/* IVG 7 */
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#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
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#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
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#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
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#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
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#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* Supplemental interrupt 1 */
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#define SYS_IRQS 71
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#define IRQ_PF0 73
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#define IRQ_PF1 74
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#define NR_MACH_IRQS (IRQ_PF47 + 1)
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/*
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* DEFAULT PRIORITIES:
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*/
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#define CONFIG_DEF_PLL_WAKEUP 7
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#define CONFIG_DEF_DMA1_ERROR 7
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#define CONFIG_DEF_DMA2_ERROR 7
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||||
#define CONFIG_DEF_IMDMA_ERROR 7
|
||||
#define CONFIG_DEF_PPI1_ERROR 7
|
||||
#define CONFIG_DEF_PPI2_ERROR 7
|
||||
#define CONFIG_DEF_SPORT0_ERROR 7
|
||||
#define CONFIG_DEF_SPORT1_ERROR 7
|
||||
#define CONFIG_DEF_SPI_ERROR 7
|
||||
#define CONFIG_DEF_UART_ERROR 7
|
||||
#define CONFIG_DEF_RESERVED_ERROR 7
|
||||
#define CONFIG_DEF_DMA1_0 8
|
||||
#define CONFIG_DEF_DMA1_1 8
|
||||
#define CONFIG_DEF_DMA1_2 8
|
||||
#define CONFIG_DEF_DMA1_3 8
|
||||
#define CONFIG_DEF_DMA1_4 8
|
||||
#define CONFIG_DEF_DMA1_5 8
|
||||
#define CONFIG_DEF_DMA1_6 8
|
||||
#define CONFIG_DEF_DMA1_7 8
|
||||
#define CONFIG_DEF_DMA1_8 8
|
||||
#define CONFIG_DEF_DMA1_9 8
|
||||
#define CONFIG_DEF_DMA1_10 8
|
||||
#define CONFIG_DEF_DMA1_11 8
|
||||
#define CONFIG_DEF_DMA2_0 9
|
||||
#define CONFIG_DEF_DMA2_1 9
|
||||
#define CONFIG_DEF_DMA2_2 9
|
||||
#define CONFIG_DEF_DMA2_3 9
|
||||
#define CONFIG_DEF_DMA2_4 9
|
||||
#define CONFIG_DEF_DMA2_5 9
|
||||
#define CONFIG_DEF_DMA2_6 9
|
||||
#define CONFIG_DEF_DMA2_7 9
|
||||
#define CONFIG_DEF_DMA2_8 9
|
||||
#define CONFIG_DEF_DMA2_9 9
|
||||
#define CONFIG_DEF_DMA2_10 9
|
||||
#define CONFIG_DEF_DMA2_11 9
|
||||
#define CONFIG_DEF_TIMER0 10
|
||||
#define CONFIG_DEF_TIMER1 10
|
||||
#define CONFIG_DEF_TIMER2 10
|
||||
#define CONFIG_DEF_TIMER3 10
|
||||
#define CONFIG_DEF_TIMER4 10
|
||||
#define CONFIG_DEF_TIMER5 10
|
||||
#define CONFIG_DEF_TIMER6 10
|
||||
#define CONFIG_DEF_TIMER7 10
|
||||
#define CONFIG_DEF_TIMER8 10
|
||||
#define CONFIG_DEF_TIMER9 10
|
||||
#define CONFIG_DEF_TIMER10 10
|
||||
#define CONFIG_DEF_TIMER11 10
|
||||
#define CONFIG_DEF_PROG0_INTA 11
|
||||
#define CONFIG_DEF_PROG0_INTB 11
|
||||
#define CONFIG_DEF_PROG1_INTA 11
|
||||
#define CONFIG_DEF_PROG1_INTB 11
|
||||
#define CONFIG_DEF_PROG2_INTA 11
|
||||
#define CONFIG_DEF_PROG2_INTB 11
|
||||
#define CONFIG_DEF_DMA1_WRRD0 8
|
||||
#define CONFIG_DEF_DMA1_WRRD1 8
|
||||
#define CONFIG_DEF_DMA2_WRRD0 9
|
||||
#define CONFIG_DEF_DMA2_WRRD1 9
|
||||
#define CONFIG_DEF_IMDMA_WRRD0 12
|
||||
#define CONFIG_DEF_IMDMA_WRRD1 12
|
||||
#define CONFIG_DEF_WATCH 13
|
||||
#define CONFIG_DEF_RESERVED_1 7
|
||||
#define CONFIG_DEF_RESERVED_2 7
|
||||
#define CONFIG_DEF_SUPPLE_0 7
|
||||
#define CONFIG_DEF_SUPPLE_1 7
|
||||
|
||||
/* IAR0 BIT FIELDS */
|
||||
#define IRQ_PLL_WAKEUP_POS 0
|
||||
#define IRQ_DMA1_ERROR_POS 4
|
||||
|
|
@ -241,6 +163,7 @@
|
|||
#define IRQ_PPI1_ERROR_POS 20
|
||||
#define IRQ_SPORT0_ERROR_POS 24
|
||||
#define IRQ_SPORT1_ERROR_POS 28
|
||||
|
||||
/* IAR1 BIT FIELDS */
|
||||
#define IRQ_SPI_ERROR_POS 0
|
||||
#define IRQ_UART_ERROR_POS 4
|
||||
|
|
@ -250,6 +173,7 @@
|
|||
#define IRQ_DMA1_2_POS 20
|
||||
#define IRQ_DMA1_3_POS 24
|
||||
#define IRQ_DMA1_4_POS 28
|
||||
|
||||
/* IAR2 BIT FIELDS */
|
||||
#define IRQ_DMA1_5_POS 0
|
||||
#define IRQ_DMA1_6_POS 4
|
||||
|
|
@ -259,6 +183,7 @@
|
|||
#define IRQ_DMA1_10_POS 20
|
||||
#define IRQ_DMA1_11_POS 24
|
||||
#define IRQ_DMA2_0_POS 28
|
||||
|
||||
/* IAR3 BIT FIELDS */
|
||||
#define IRQ_DMA2_1_POS 0
|
||||
#define IRQ_DMA2_2_POS 4
|
||||
|
|
@ -268,6 +193,7 @@
|
|||
#define IRQ_DMA2_6_POS 20
|
||||
#define IRQ_DMA2_7_POS 24
|
||||
#define IRQ_DMA2_8_POS 28
|
||||
|
||||
/* IAR4 BIT FIELDS */
|
||||
#define IRQ_DMA2_9_POS 0
|
||||
#define IRQ_DMA2_10_POS 4
|
||||
|
|
@ -277,6 +203,7 @@
|
|||
#define IRQ_TIMER2_POS 20
|
||||
#define IRQ_TIMER3_POS 24
|
||||
#define IRQ_TIMER4_POS 28
|
||||
|
||||
/* IAR5 BIT FIELDS */
|
||||
#define IRQ_TIMER5_POS 0
|
||||
#define IRQ_TIMER6_POS 4
|
||||
|
|
@ -286,6 +213,7 @@
|
|||
#define IRQ_TIMER10_POS 20
|
||||
#define IRQ_TIMER11_POS 24
|
||||
#define IRQ_PROG0_INTA_POS 28
|
||||
|
||||
/* IAR6 BIT FIELDS */
|
||||
#define IRQ_PROG0_INTB_POS 0
|
||||
#define IRQ_PROG1_INTA_POS 4
|
||||
|
|
@ -295,6 +223,7 @@
|
|||
#define IRQ_DMA1_WRRD0_POS 20
|
||||
#define IRQ_DMA1_WRRD1_POS 24
|
||||
#define IRQ_DMA2_WRRD0_POS 28
|
||||
|
||||
/* IAR7 BIT FIELDS */
|
||||
#define IRQ_DMA2_WRRD1_POS 0
|
||||
#define IRQ_IMDMA_WRRD0_POS 4
|
||||
|
|
@ -305,4 +234,4 @@
|
|||
#define IRQ_SUPPLE_0_POS 24
|
||||
#define IRQ_SUPPLE_1_POS 28
|
||||
|
||||
#endif /* _BF561_IRQ_H_ */
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue