x86, insn: Add new opcodes as of June, 2013
Add TSX-NI related instructions and new instructions to x86-opcode-map.txt according to the Intel(R) 64 and IA-32 Architectures Software Developer's Manual Vol2C (June, 2013). This also includes below updates. - Fix a typo of MWAIT (the lack of (11B)). - Change NOP Ev to prefetchw Ev - Add CRC32 new prefix style (66&F2) - Add ADCX, ADOX, RDSEED, CLAC and STAC instructions Signed-off-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Link: http://lkml.kernel.org/r/20130806073750.4049.12365.stgit@udc4-manage.rcp.hitachi.co.jp Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>hifive-unleashed-5.1
Masami Hiramatsu
H. Peter Anvin
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@ -1,10 +1,8 @@
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# x86 Opcode Maps
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#
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# This is (mostly) based on following documentations.
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# - Intel(R) 64 and IA-32 Architectures Software Developer's Manual Vol.2
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# (#325383-040US, October 2011)
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# - Intel(R) Advanced Vector Extensions Programming Reference
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# (#319433-011,JUNE 2011).
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# - Intel(R) 64 and IA-32 Architectures Software Developer's Manual Vol.2C
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# (#326018-047US, June 2013)
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#
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#<Opcode maps>
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# Table: table-name
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@ -29,6 +27,7 @@
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# - (F3): the last prefix is 0xF3
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# - (F2): the last prefix is 0xF2
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# - (!F3) : the last prefix is not 0xF3 (including non-last prefix case)
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# - (66&F2): Both 0x66 and 0xF2 prefixes are specified.
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Table: one byte opcode
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Referrer:
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@ -246,8 +245,8 @@ c2: RETN Iw (f64)
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c3: RETN
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c4: LES Gz,Mp (i64) | VEX+2byte (Prefix)
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c5: LDS Gz,Mp (i64) | VEX+1byte (Prefix)
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c6: Grp11 Eb,Ib (1A)
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c7: Grp11 Ev,Iz (1A)
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c6: Grp11A Eb,Ib (1A)
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c7: Grp11B Ev,Iz (1A)
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c8: ENTER Iw,Ib
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c9: LEAVE (d64)
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ca: RETF Iw
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@ -293,8 +292,8 @@ ef: OUT DX,eAX
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# 0xf0 - 0xff
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f0: LOCK (Prefix)
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f1:
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f2: REPNE (Prefix)
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f3: REP/REPE (Prefix)
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f2: REPNE (Prefix) | XACQUIRE (Prefix)
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f3: REP/REPE (Prefix) | XRELEASE (Prefix)
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f4: HLT
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f5: CMC
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f6: Grp3_1 Eb (1A)
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@ -326,7 +325,8 @@ AVXcode: 1
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0a:
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0b: UD2 (1B)
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0c:
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0d: NOP Ev | GrpP
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# AMD's prefetch group. Intel supports prefetchw(/1) only.
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0d: GrpP
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0e: FEMMS
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# 3DNow! uses the last imm byte as opcode extension.
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0f: 3DNow! Pq,Qq,Ib
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@ -729,12 +729,12 @@ dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
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dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
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de: VAESDEC Vdq,Hdq,Wdq (66),(v1)
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df: VAESDECLAST Vdq,Hdq,Wdq (66),(v1)
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f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2)
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f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2)
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f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) | CRC32 Gd,Eb (66&F2)
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f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)
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f2: ANDN Gy,By,Ey (v)
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f3: Grp17 (1A)
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f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
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f6: MULX By,Gy,rDX,Ey (F2),(v)
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f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
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f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
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EndTable
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@ -861,8 +861,8 @@ EndTable
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GrpTable: Grp7
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0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
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1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001)
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2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B)
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1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
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2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
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3: LIDT Ms
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4: SMSW Mw/Rv
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5:
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@ -880,15 +880,21 @@ EndTable
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GrpTable: Grp9
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1: CMPXCHG8B/16B Mq/Mdq
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6: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B)
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7: VMPTRST Mq | VMPTRST Mq (F3)
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7: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B)
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EndTable
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GrpTable: Grp10
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EndTable
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GrpTable: Grp11
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# Note: the operands are given by group opcode
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0: MOV
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# Grp11A and Grp11B are expressed as Grp11 in Intel SDM
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GrpTable: Grp11A
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0: MOV Eb,Ib
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7: XABORT Ib (000),(11B)
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EndTable
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GrpTable: Grp11B
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0: MOV Eb,Iz
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7: XBEGIN Jz (000),(11B)
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EndTable
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GrpTable: Grp12
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@ -68,7 +68,7 @@ BEGIN {
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lprefix1_expr = "\\((66|!F3)\\)"
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lprefix2_expr = "\\(F3\\)"
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lprefix3_expr = "\\((F2|!F3)\\)"
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lprefix3_expr = "\\((F2|!F3|66\\&F2)\\)"
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lprefix_expr = "\\((66|F2|F3)\\)"
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max_lprefix = 4
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@ -83,6 +83,8 @@ BEGIN {
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prefix_num["Operand-Size"] = "INAT_PFX_OPNDSZ"
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prefix_num["REPNE"] = "INAT_PFX_REPNE"
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prefix_num["REP/REPE"] = "INAT_PFX_REPE"
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prefix_num["XACQUIRE"] = "INAT_PFX_REPNE"
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prefix_num["XRELEASE"] = "INAT_PFX_REPE"
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prefix_num["LOCK"] = "INAT_PFX_LOCK"
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prefix_num["SEG=CS"] = "INAT_PFX_CS"
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prefix_num["SEG=DS"] = "INAT_PFX_DS"
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